For hardware synthesis, there are two types of always blocks that are relevant:
- Combinational: always @(*)
- Clocked: always @(posedge clk)
Clocked always blocks create a blob of combinational logic just like combinational always blocks, but also creates a set of flip-flops (or "registers") at the output of the blob of combinational logic. Instead of the outputs of the blob of logic being visible immediately, the outputs are visible only immediately after the next (posedge clk).
Blocking vs. Non-Blocking Assignment
There are three types of assignments in Verilog:
- Continuous assignments (assign x = y;). Can only be used when not inside a procedure ("always block").
- Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
- Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.
In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments. A full understanding of why is not particularly useful for hardware design and requires a good understanding of how Verilog simulators keep track of events. Not following this rule results in extremely hard to find errors that are both non-deterministic and differ between simulation and synthesized hardware.
对于硬件合成，有两种相关的always块类型：
组合型：always @(*)
时钟型：always @(posedge clk)
时钟型always块创建了一个与组合型always块类似的组合逻辑块，但还在组合逻辑块的输出处创建了一组触发器（或"寄存器"）。与组合逻辑块的输出立即可见不同，输出只在下一个（posedge clk）之后立即可见。
阻塞式赋值和非阻塞式赋值
Verilog中有三种类型的赋值：
连续赋值（continuous assignments）（assign x = y;）。仅在不在过程（"always block"）中使用时可用。
过程阻塞式赋值：（x = y;）。仅在过程中使用时可用。
过程非阻塞式赋值：（x <= y;）。仅在过程中使用时可用。
在组合型always块中使用阻塞式赋值，在时钟型always块中使用非阻塞式赋值。要完全理解其中原因对于硬件设计并不特别有用，而且需要对Verilog仿真器如何跟踪事件有一定的了解。不遵循此规则会导致非确定性且在仿真和合成的硬件之间不同的极难发现的错误。