[HDLBits] Mt2015 lfsr

向盟约宣誓2023-09-25 11:50

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.

复制代码

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
	wire result;
    parts part1(KEY[0],KEY[1],SW[0],LEDR[2],LEDR[0]);
    parts part2(KEY[0],KEY[1],SW[1],LEDR[0],LEDR[1]);
    assign result=LEDR[2]^LEDR[1];
    parts part3(KEY[0],KEY[1],SW[2],result,LEDR[2]);
endmodule
        
        
module parts(
	input clk,
	input l,
	input r,
    input q1,
    output Q);
    wire d;
    assign d=l?r:q1;
    always@(posedge clk) begin
        Q<=d;
    end
endmodule