[HDLBits] Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

Left Center Right Center's next state
1 1 1 0
1 1 0 1
1 0 1 0
1 0 0 1
0 1 1 1
0 1 0 0
0 0 1 1
0 0 0 0

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

复制代码
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
        //verilog最好的地方就是支持整个数组批量运算
    end
endmodule

verilog真舒服

相关推荐
坏孩子的诺亚方舟2 小时前
FPGA系统架构设计实践7_时序收敛作业概述
fpga·xilinx·时序收敛·作业流程
嵌入式软硬件攻城狮6 小时前
2.FPGA板卡通过电脑映射连接上网
fpga开发·电脑
brave and determined7 小时前
可编程逻辑器件学习(day22):“让ARM穿上FPGA的马甲“:赛灵思Zynq的命名哲学与技术革命
arm开发·嵌入式硬件·fpga开发·zynq·fpga设计·嵌入式设计·fpga开发流程
FPGA_小田老师1 天前
FPGA语法基础(二):SystemVerilog 数组清零方法详解
fpga开发·systemverilog·数组清零·systemverilog数组·systemverilog语法
jiushun_suanli1 天前
FPGA(现场可编程门阵列)详解
经验分享·学习·fpga开发
Terasic友晶科技1 天前
1-串行通信基础知识
fpga开发·串口通信·异步通信·串行通信·同步通信·并行通信·单工
FPGA_小田老师1 天前
Xilinx Aurora 8B/10B IP核(2):Shared Logic的选择
fpga开发·aurora 8b/10b·share logic·aurora接口
嵌入式软硬件攻城狮1 天前
4.FPGA字符格式
fpga开发
Terasic友晶科技1 天前
2-基于FPGA开发板DE23-Lite的串口通信设计 (FT2232H)
fpga开发·串口·uart·de23-lite
第二层皮-合肥2 天前
FPGA工程师12实战项目-基于PCIe的高速ADC采集项目
fpga开发