[HDLBits] Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

Left Center Right Center's next state
1 1 1 0
1 1 0 1
1 0 1 0
1 0 0 1
0 1 1 1
0 1 0 0
0 0 1 1
0 0 0 0

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

复制代码
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
        //verilog最好的地方就是支持整个数组批量运算
    end
endmodule

verilog真舒服

相关推荐
南檐巷上学13 小时前
Vivado调用FFT IP核进行数据频谱分析
fpga开发·fpga·vivado·fft·快速傅里叶变化
奋斗的牛马17 小时前
FPGA—ZYNQ学习Helloward(二)
单片机·嵌入式硬件·学习·fpga开发
FPGA_小田老师1 天前
FPGA调试利器:JTAG to AXI Master IP核详解与实战演练
fpga开发·jtag测试·jtag2axi ip·ddr3自动化
FPGA_小田老师1 天前
FPGA开发入门:深入理解计数器——数字逻辑的时序基石
fpga开发·verilog·状态机·计数器·计数器设计
碎碎思1 天前
用 FPGA 实现 PCIe 传输,开源核 LitePCIe 深度解读
fpga开发
9527华安1 天前
FPGA纯verilog实现JESD204B协议,基于AD9625数据接收,提供2套工程源码和技术支持
fpga开发·jesd204b·ad9625
Shang180989357261 天前
MS2107高性能USB 2.0视频信号和音频采集,支持NTSC/PAL制式,适用于低成本视频采集设备
嵌入式硬件·fpga开发·音视频·硬件工程·信息与通信·dsp开发
学工科的皮皮志^_^1 天前
网口学习理解
经验分享·笔记·嵌入式硬件·学习·fpga开发·以太网
博览鸿蒙2 天前
FPGA高频面试问题整理—附答案
fpga开发
cmc10282 天前
134.FPGA常见管脚与时钟的约束方法
fpga开发