[HDLBits] Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

Left Center Right Center's next state
1 1 1 0
1 1 0 1
1 0 1 0
1 0 0 1
0 1 1 1
0 1 0 0
0 0 1 1
0 0 0 0

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

复制代码
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
        //verilog最好的地方就是支持整个数组批量运算
    end
endmodule

verilog真舒服

相关推荐
GateWorld11 小时前
深入浅出IIC协议 - 从总线原理到FPGA实战开发 -- 第一篇:I2C总线协议深度解剖
fpga开发·开源协议
爱学习的张哥13 小时前
UDP--DDR--SFP,FPGA实现之模块梳理及AXI读写DDR读写上板测试
单片机·fpga开发·udp·axi·ddr
白杨树田17 小时前
【EDA软件】【联合Modelsim仿真使用方法】
fpga开发
搬砖的小码农_Sky18 小时前
FPGA: XILINX Kintex 7系列器件的架构
fpga开发·架构·硬件架构
搬砖的小码农_Sky1 天前
FPGA:如何提高RTL编码能力?
fpga开发·硬件架构
晶台光耦1 天前
高速光耦在通信行业的应用(五) | 5Mbps通信光耦的特性
fpga开发
梓仁沐白1 天前
Verilog HDL 语言整理
fpga开发
FPGA_ADDA1 天前
基于PXIE 总线架构的Kintex UltraScale 系列FPGA 高性能数据预处理板卡
fpga开发·pxie总线·ku060·ku115
搬砖的小码农_Sky2 天前
FPGA:Lattice的FPGA产品线以及器件选型建议
嵌入式硬件·fpga开发·硬件架构·硬件工程
超能力MAX2 天前
ZYNQ-AXI4 DDR读写测试
fpga开发