[HDLBits] Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

Left Center Right Center's next state
1 1 1 0
1 1 0 1
1 0 1 0
1 0 0 1
0 1 1 1
0 1 0 0
0 0 1 1
0 0 0 0

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)

In this circuit, create a 512-cell system (q511:0), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data511:0. Assume the boundaries (q-1 and q512) are both zero (off).

复制代码
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
        //verilog最好的地方就是支持整个数组批量运算
    end
endmodule

verilog真舒服

相关推荐
minglie13 小时前
j2b描述smp协议
fpga开发
FPGA开源工坊7 小时前
FPGA开发技巧–BRAM资源优化
fpga开发
泛联新安15 小时前
InfinitPro多FPGA原型验证系统|提升芯片设计验证效率10-100倍
fpga开发
hahaha60161 天前
HLS高层次综合设计技巧--数组
开发语言·嵌入式硬件·算法·fpga开发
NamoAmitabha1281 天前
直接上手 UVM 例子
fpga开发
cmc10282 天前
301.modelsim自动仿真
fpga开发
Riwuarua2 天前
从近似0基础开始FPGA开发 -- part.10 verilog-ethernet开源UDP协议栈工程学习
fpga开发·udp·开源
my_daling2 天前
紫光FPGA远程升级注意事项(关于GTP_CFGCLK原语使用问题)
笔记·学习·fpga开发
Riwuarua3 天前
从近似0基础开始FPGA开发 -- part.11 AXI总线协议与工程应用
fpga开发
自小吃多3 天前
高云 FPGA 添加时序约束笔记
笔记·fpga开发