[HDLBits] Rule90

Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:

Left Center Right Center's next state
1 1 1 0
1 1 0 1
1 0 1 0
1 0 0 1
0 1 1 1
0 1 0 0
0 0 1 1
0 0 0 0

(The name "Rule 90" comes from reading the "next state" column: 01011010 is decimal 90.)

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

复制代码
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
        //verilog最好的地方就是支持整个数组批量运算
    end
endmodule

verilog真舒服

相关推荐
gaoxcv16 小时前
TDC相关的一些方法
fpga开发
我爱C编程16 小时前
【3.4】双口RAM模块的FPGA实现
fpga开发·fpga·fft·双口ram
三万棵雪松16 小时前
【嵌入式刷题硬件设计基础(一)】
fpga开发·嵌入式·硬件基础
扣脑壳的FPGAer17 小时前
Xilinx远程更新之watchdog Timer1/ Timer2
fpga开发
ALINX技术博客17 小时前
【黑金云课堂】FPGA技术教程Linux开发:Petalinux安装
linux·运维·fpga开发
豆包公子1 天前
虚拟机配置共享文件&烧录FPGA bit文件
fpga开发
c-u-r-ry301 天前
pll/mmcm输入时钟配置页面警告
经验分享·fpga开发
逻辑诗篇1 天前
硬核算力集结!TMS320C6678、XC7K690T等、匠行科技SBC819模拟信号采集处理板,解锁高端测控新标杆
科技·fpga开发
狂奔蜗牛(bradley)2 天前
FPGA基础知识:深度剖析异步复位同步释放
fpga开发
发发就是发2 天前
USB系统架构概述:从一次诡异的枚举失败说起
驱动开发·单片机·嵌入式硬件·算法·fpga开发