「HDLBits题解」Arithmetic Circuits

正在黑化的KS2024-01-18 0:35

本专栏的目的是分享可以通过HDLBits仿真的Verilog代码以提供参考各位可同时参考我的代码和官方题解代码或许会有所收益

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module top_module( 
    input a, b,
    output cout, sum );
	assign cout = a & b ; 
    assign sum = a ^ b ;
endmodule

题目链接：Fadd - HDLBits

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module top_module( 
    input a, b, cin,
    output cout, sum );
	assign sum = a ^ b ^ cin ; 
    assign cout = (a & b) | (a & cin) | (b & cin) ; 
endmodule

题目链接： Adder3 - HDLBits

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module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );

    add1 u0(a[0], b[0], cin, sum[0], cout[0]) ;
    add1 u1(a[1], b[1], cout[0], sum[1], cout[1]) ;
    add1 u2(a[2], b[2], cout[1], sum[2], cout[2]) ;

endmodule


module add1 ( input a, input b, input cin, output sum, output cout );
 
// Full adder module here
    assign sum = a ^ b ^ cin ; 
    assign cout = (a & b) | (a & cin) | (b & cin) ; 
endmodule

题目链接：Exams/m2014 q4j - HDLBits

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module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);

    wire [4:0] cout ; 

    add1 u0(x[0], y[0], 0, sum[0], cout[0]) ;
    add1 u1(x[1], y[1], cout[0], sum[1], cout[1]) ;
    add1 u2(x[2], y[2], cout[1], sum[2], cout[2]) ;
    add1 u3(x[3], y[3], cout[2], sum[3], cout[3]) ;

    assign sum[4] = cout[3] ;

endmodule


module add1 ( input a, input b, input cin, output sum, output cout );
 
// Full adder module here
    assign sum = a ^ b ^ cin ; 
    assign cout = (a & b) | (a & cin) | (b & cin) ; 
endmodule

题目链接：Exams/ece241 2014 q1c - HDLBits

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module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
    // assign s = ...
    // assign overflow = ...
    assign s = a + b ;
    assign overflow = (~(a[7] ^ b[7])) & (s[7] != a[7]); 

endmodule

题目链接：Adder100 - HDLBits

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module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
	assign {cout, sum} = a + b + cin ;
endmodule

题目链接：Bcdadd4 - HDLBits

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module top_module ( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum 
); 
    wire [3:0] temp ; 

    bcd_fadd u0(a[3:0], b[3:0], cin, temp[0], sum[3:0]) ;
    bcd_fadd u1(a[7:4], b[7:4], temp[0], temp[1], sum[7:4]) ;
    bcd_fadd u2(a[11:8], b[11:8], temp[1], temp[2], sum[11:8]) ;
    bcd_fadd u3(a[15:12], b[15:12], temp[2], temp[3], sum[15:12]) ;

    assign cout = temp[3];

endmodule