50.TFT_LCD液晶屏驱动设计与验证（3）

（1）数据生成模块Verilog代码：

module data_gen(
    input   [9:0]   hang        ,
    input   [9:0]   lie         ,
    input           clk_33M     ,
    input           reset_n     ,
    
    output  reg     [23:0]  data    
);
//定义最大行、列
    parameter HANG_MAX  = 800   ;
    parameter LIE_MAX   = 480   ;
    
//定义颜色
    parameter RED       =   24'hff0000;
    parameter ORANGE    =   24'hffcc66;
    parameter YELLOW    =   24'hffff00;
    parameter GREEN     =   24'h33cc33;
    parameter CYAN      =   24'h00ffcc;
    parameter BLUE      =   24'h3333ff;
    parameter PUPPLE    =   24'hcc00cc;
    parameter BLACK     =   24'h000000;
    parameter WHITE     =   24'hffffff;
    parameter GRAY      =   24'hb2b2b2;

//数据生成设计
    always@(posedge clk_33M or negedge reset_n)
        if(!reset_n)
            data <= BLACK   ;
        else if((hang >= 1) && (hang <= HANG_MAX/10))
            data <= RED     ;
        else if((hang > HANG_MAX/10) && (hang <= (HANG_MAX/10) * 2))
            data <= ORANGE  ;
        else if((hang > (HANG_MAX/10) * 2) && (hang <= (HANG_MAX/10) * 3))
            data <= YELLOW  ;
        else if((hang > (HANG_MAX/10) * 3) && (hang <= (HANG_MAX/10) * 4))
            data <= GREEN  ;
        else if((hang > (HANG_MAX/10) * 4) && (hang <= (HANG_MAX/10) * 5))
            data <= CYAN  ;
        else if((hang > (HANG_MAX/10) * 5) && (hang <= (HANG_MAX/10) * 6))
            data <= BLUE  ;
        else if((hang > (HANG_MAX/10) * 6) && (hang <= (HANG_MAX/10) * 7))
            data <= PUPPLE  ;
        else if((hang > (HANG_MAX/10) * 7) && (hang <= (HANG_MAX/10) * 8))
            data <= BLACK  ;
        else if((hang > (HANG_MAX/10) * 8) && (hang <= (HANG_MAX/10) * 9))
            data <= WHITE  ;
        else if((hang > (HANG_MAX/10) * 9) && (hang <= HANG_MAX))
            data <= GRAY   ;
        else
            data <= BLACK  ;
            
endmodule

（2）仿真文件：

`timescale 1ns / 1ps

module data_gen_tb;

reg             clk         ;
reg             reset_n     ;

wire    [23:0]  data        ;
wire    [23:0]  data_in     ;
    
wire            locked      ;
wire            clk_33M     ;

wire    [9:0]   hang        ;
wire    [9:0]   lie         ;    
wire            hsync       ;   
wire            vsync       ;
wire    [23:0]  rgb_tft     ;
wire            tft_bl      ;
wire            tft_clk     ;
wire            tft_DE      ;

initial clk = 1'd1;
always #10 clk = ~clk;

initial begin
        reset_n <= 1'd0;
        #15;
        reset_n <= 1'd1;
        #20_000_000;
        $stop;
end

assign data_in = data  ;

PLL_33M     PLL_33M_inst
(

    .clk_33M        (clk_33M    ), 

    .resetn         (reset_n    ), 
    .locked         (locked     ), 
    .clk_in1        (clk        )
);

tft_ctrl    tft_ctrl_inst
(
    .clk_33M         (clk_33M   ),
    .reset_n         (locked    ),
    .data_in         (data_in   ),

    .hang            (hang      ),
    .lie             (lie       ),
    .hsync           (hsync     ),
    .vsync           (vsync     ),
    .rgb_tft         (rgb_tft   ),
    .tft_bl          (tft_bl    ),
    .tft_clk         (tft_clk   ),
    .tft_DE          (tft_DE    )
);

data_gen    data_gen_inst
(
    .hang        (hang),
    .lie         (lie),
    .clk_33M     (clk_33M),
    .reset_n     (locked),

    .data        (data)
);

endmodule

（3）仿真波形：