c
复制代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/08/20 16:32:39
// Design Name:
// Module Name: thetas
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module thetas(
clk,
rst,
theta,
o_real_k,
o_imag_k
);
input clk;
input rst;
input [7:0] theta;
output [7:0] o_real_k;
output [7:0] o_imag_k;
wire [18 : 0] P_hudu;// A * 0.0175 * 2^16
mult_hudu_8_1143 mult_hudu_8_1143 (
.CLK(clk), // input wire CLK
.A(theta), // input wire [7 : 0] A
.P(P_hudu) // output wire [18 : 0] P Q3.16
);
wire [31 : 0] m_axis_dout_tdata;
see_hudu see_hudu (
.aclk(clk), // input wire aclk
.aclken(1'b1), // input wire aclken
.aresetn(~rst), // input wire aresetn
.s_axis_phase_tvalid(1'b1), // input wire s_axis_phase_tvalid
.s_axis_phase_tdata(P_hudu[18:3]), // input wire [15 : 0] s_axis_phase_tdata
.m_axis_dout_tvalid( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [31 : 0] m_axis_dout_tdata
);
wire [31 : 0] real_k,imag_k;
cmpy_8_16 cmpy_8_16 (
.aclk(clk), // input wire aclk
.aclken(1'b1), // input wire aclken
.aresetn(~rst), // input wire aresetn
.s_axis_a_tvalid(1'b1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({8'd90,8'd90}), // input wire [15 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'b1), // input wire s_axis_b_tvalid
.s_axis_b_tdata(m_axis_dout_tdata), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata({imag_k,real_k}) // output wire [63 : 0] m_axis_dout_tdata
);
assign o_real_k = real_k[21:14];
assign o_imag_k = imag_k[21:14];
endmodule