状态机思想编程

1. LED流水灯的FPGA代码

一个使用状态机思想来实现LED流水灯的FPGA代码

这个例子采用VHDL编写

VHDL代码示例：

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led_flowing is
    Port ( clk   : in  std_logic;
           reset : in  std_logic;
           led   : out std_logic_vector(7 downto 0));
end led_flowing;

architecture Behavioral of led_flowing is
    type state_type is (s0, s1, s2, s3, s4, s5, s6, s7);
    signal current_state, next_state : state_type;
    signal count : integer := 0;
    
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= s0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process(current_state)
    begin
        case current_state is
            when s0 =>
                led <= "00000001";  -- 灯1亮
                next_state <= s1;
            when s1 =>
                led <= "00000010";  -- 灯2亮
                next_state <= s2;
            when s2 =>
                led <= "00000100";  -- 灯3亮
                next_state <= s3;
            when s3 =>
                led <= "00001000";  -- 灯4亮
                next_state <= s4;
            when s4 =>
                led <= "00010000";  -- 灯5亮
                next_state <= s5;
            when s5 =>
                led <= "00100000";  -- 灯6亮
                next_state <= s6;
            when s6 =>
                led <= "01000000";  -- 灯7亮
                next_state <= s7;
            when s7 =>
                led <= "10000000";  -- 灯8亮
                next_state <= s0;
            when others =>
                led <= "00000000";  -- 关闭所有灯
                next_state <= s0;
        end case;
    end process;

end Behavioral;

仿真测试代码：

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_led_flowing is
end tb_led_flowing;

architecture Behavioral of tb_led_flowing is

    signal clk   : std_logic := '0';
    signal reset : std_logic := '0';
    signal led   : std_logic_vector(7 downto 0);

    constant CLK_PERIOD : time := 10 ns;

begin

    uut: entity work.led_flowing
        port map (
            clk => clk,
            reset => reset,
            led => led
        );

    -- Clock generation
    clk_process :process
    begin
        while True loop
            clk <= '0';
            wait for CLK_PERIOD/2;
            clk <= '1';
            wait for CLK_PERIOD/2;
        end loop;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
        reset <= '1';
        wait for 20 ns;
        reset <= '0';
        wait for 300 ns; -- 放置足够的时间进行观察
        assert false report "End of simulation" severity note;
        wait;
    end process;

end Behavioral;

流水灯演示：

2. CPLD和FPGA芯片的主要技术区别

CPLD（复杂可编程逻辑器件）与FPGA（现场可编程门阵列）的主要区别：

1、结构与规模：

CPLD ：通常具有较小的逻辑单元和较低的延迟，适合简单的组合逻辑和小规模状态机。FPGA：具有较大的逻辑块（逻辑单元），可以支持更复杂的设计和更高的并行处理能力。

2、应用场合：

CPLD ：适合用于控制逻辑、状态机、小型接口或数据处理，通常用于低功耗、高速的应用。244FPGA：适用于需要处理大量并行信号和复杂算法的应用，如图像处理、数据加速等。