概述
本文主要描述了在Qemu平台中，如何添加STM32F103的RCC控制器模拟代码。
参考资料
STM32F1XX TRM手册，手册编号：RM0008
添加步骤
1、在hw/arm/Kconfig文件中添加STM32F1XX_RCC，如下所示:
+号部分为新增加内容
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 85c93cdf..7fffae5e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -413,6 +413,7 @@ config STM32F103_SOC
bool
select ARM_V7M
select OR_IRQ
+ select STM32F1XX_RCC2、在include/hw/arm/stm32f103_soc.h文件中添加
+号部分为新增加内容
diff --git a/include/hw/arm/stm32f103_soc.h b/include/hw/arm/stm32f103_soc.h
index 182fe14b..f9800544 100644
--- a/include/hw/arm/stm32f103_soc.h
+++ b/include/hw/arm/stm32f103_soc.h
@@ -23,6 +23,7 @@
#include "hw/or-irq.h"
#include "hw/arm/armv7m.h"
+#include "hw/misc/stm32f1xx_rcc.h"
#define FLASH_BASE_ADDRESS 0x8000000
@@ -30,6 +31,8 @@
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (20 * 1024)
+#define RCC_BASE_ADDR 0x40021000
+
#define TYPE_STM32F103_SOC "stm32f103-soc"
#define STM32F103_SOC(obj) \
OBJECT_CHECK(STM32F103State, (obj), TYPE_STM32F103_SOC)
@@ -43,6 +46,8 @@ typedef struct STM32F103State {
char *cpu_type;
ARMv7MState armv7m;
+ STM32F1XXRccState rcc;
+
} STM32F103State;
#endif3、在hw/arm/stm32f103_soc.c文件中添加如下代码片段
+号部分为新增加内容
diff --git a/hw/arm/stm32f103_soc.c b/hw/arm/stm32f103_soc.c
index b072855e..8155c4ae 100644
--- a/hw/arm/stm32f103_soc.c
+++ b/hw/arm/stm32f103_soc.c
@@ -39,12 +39,16 @@ static void stm32f103_soc_initfn(Object *obj)
sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
TYPE_ARMV7M);
+
+ object_initialize(&s->rcc, sizeof(s->rcc), TYPE_STM32F1XX_RCC);
+ qdev_set_parent_bus(DEVICE(&s->rcc), sysbus_get_default());
}
static void stm32f103_soc_realize(DeviceState *dev_soc, Error **errp)
{
STM32F103State *s = STM32F103_SOC(dev_soc);
- DeviceState *armv7m;
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
Error *err = NULL;
armv7m = DEVICE(&s->armv7m);
@@ -58,6 +62,15 @@ static void stm32f103_soc_realize(DeviceState *dev_soc, Error **errp)
error_propagate(errp, err);
return;
}
+ /* System rcc controller */
+ dev = DEVICE(&s->rcc);
+ object_property_set_bool(OBJECT(&s->rcc), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, RCC_BASE_ADDR);
}4.在hw/miscKconfig中添加
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index f5218dc0..b0dfe0bb 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -101,6 +101,9 @@ config IMX
select SSI
select USB_EHCI_SYSBUS
+config STM32F1XX_RCC
+ bool
+5.在hw/misc/Makefile.objs中添加
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 2d700747..b6f02ea1 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -65,6 +65,7 @@ common-obj-$(CONFIG_SLAVIO) += slavio_misc.o
common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o
common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o
common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
+common-obj-$(CONFIG_STM32F1XX_RCC) += stm32f1xx_rcc.o
obj-$(CONFIG_STM32F4XX_RCC) += stm32f4xx_rcc.o
obj-$(CONFIG_STM32F4XX_PWR) += stm32f4xx_pwr.o
obj-$(CONFIG_STM32F4XX_FLASH) += stm32f4xx_flash.o6.在hw/misc/创建新文件stm32f1xx_rcc.c
diff --git a/hw/misc/stm32f1xx_rcc.c b/hw/misc/stm32f1xx_rcc.c
new file mode 100644
index 00000000..7232b2b9
--- /dev/null
+++ b/hw/misc/stm32f1xx_rcc.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2025 liang yan <[email protected]>
+ *
+ * STM32F1XX RCC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#include "qemu/osdep.h"
+#include "hw/misc/stm32f1xx_rcc.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qemu/module.h"
+#include "migration/vmstate.h"
+#include "hw/timer/armv7m_systick.h"
+#include "qemu/timer.h"
+
+#ifndef STM_RCC_ERR_DEBUG
+#define STM_RCC_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_RCC_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+static void stm32f1xx_rcc_reset(DeviceState *dev)
+{
+ STM32F1XXRccState *s = STM32F1XX_RCC(dev);
+
+ s->rcc_cr = 0x00000083;
+ s->rcc_cfgr = 0x00000000;
+ s->rcc_cir = 0x00000000;
+ s->rcc_apb2rstr = 0x00000000;
+ s->rcc_apb1rstr = 0x00000000;
+ s->rcc_ahbenr = 0x00000014;
+ s->rcc_apb2enr = 0x00000000;
+ s->rcc_apb1enr = 0x00000000;
+ s->rcc_bdcr = 0x00000000;
+ s->rcc_csr = 0x0c000000;
+}
+
+static uint64_t stm32f1xx_rcc_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F1XXRccState *s = opaque;
+ uint64_t reg = 0;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+ switch (addr) {
+ case RCC_CR:
+ reg = s->rcc_cr;
+ break;
+ case RCC_CFGR:
+ reg = s->rcc_cfgr;
+ break;
+ case RCC_CIR:
+ reg = s->rcc_cir;
+ break;
+ case RCC_APB2RSTR:
+ reg = s->rcc_apb2rstr;
+ break;
+ case RCC_APB1RSTR:
+ reg = s->rcc_apb1rstr;
+ break;
+ case RCC_AHBENR:
+ reg = s->rcc_ahbenr;
+ break;
+ case RCC_APB2ENR:
+ reg = s->rcc_apb2enr;
+ break;
+ case RCC_APB1ENR:
+ reg = s->rcc_apb1enr;
+ break;
+ case RCC_BDCR:
+ reg = s->rcc_bdcr;
+ break;
+ case RCC_CSR:
+ reg = s->rcc_csr;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ reg = 0;
+ }
+ return reg;
+}
+
+static void stm32f1xx_rcc_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F1XXRccState *s = opaque;
+ uint32_t value = val64;
+ uint32_t pll_mutil;
+ uint32_t cpu_freq_hz = 0;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
+ switch (addr) {
+ case RCC_CR:
+ s->rcc_cr = value;
+ if (value & RCC_CR_HSION)
+ s->rcc_cr |= RCC_CR_HSIRDY;
+ else
+ s->rcc_cr &= ~RCC_CR_HSIRDY;
+ if (value & RCC_CR_HSENON)
+ s->rcc_cr |= RCC_CR_HSERDY;
+ else
+ s->rcc_cr &= ~RCC_CR_HSIRDY;
+ if (value & RCC_CR_PLLON)
+ s->rcc_cr |= RCC_CR_PLLRDY;
+ else
+ s->rcc_cr &= ~RCC_CR_PLLRDY;
+ break;
+ case RCC_CFGR:
+ s->rcc_cfgr = value;
+ /* setup system clock source */
+ if (value & RCC_CFGR_SW_PLL)
+ s->rcc_cfgr |= RCC_CFGR_SWS_PLL;
+ else if (value & RCC_CFGR_SW_HSE)
+ s->rcc_cfgr |= RCC_CFGR_SWS_HSE;
+ else
+ s->rcc_cfgr |= RCC_CFGR_SWS_HSI;
+ /* setup system clock */
+ if ((value & RCC_CFGR_SW_PLL) || (value & RCC_CFGR_SW_HSE))
+ cpu_freq_hz = 8000000;
+ else {
+ pll_mutil = ((value >> 18) & 0xf) + 2;
+ if ((s->rcc_cfgr & RCC_CFGR_SWS_HSI)) {
+ cpu_freq_hz = (8 / 2) * pll_mutil * 1000000;
+ }
+ else
+ {
+ if (value & RCC_CFGR_PLLXTPRE)
+ cpu_freq_hz = (8 / 2) * pll_mutil * 1000000;
+ else
+ cpu_freq_hz = 8 * pll_mutil * 1000000;
+ }
+ }
+
+ if (cpu_freq_hz) {
+ system_clock_scale = NANOSECONDS_PER_SECOND / cpu_freq_hz;
+ if (system_clock_scale == 0)
+ system_clock_scale = 1;
+ }
+ break;
+ case RCC_CIR:
+ s->rcc_cir = value;
+ break;
+ case RCC_APB2RSTR:
+ s->rcc_apb2rstr = value;
+ break;
+ case RCC_APB1RSTR:
+ s->rcc_apb1rstr = value;
+ break;
+ case RCC_AHBENR:
+ s->rcc_ahbenr = value;
+ break;
+ case RCC_APB2ENR:
+ s->rcc_apb2enr = value;
+ break;
+ case RCC_APB1ENR:
+ s->rcc_apb1enr = value;
+ break;
+ case RCC_BDCR:
+ s->rcc_bdcr = value;
+ break;
+ case RCC_CSR:
+ s->rcc_csr = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f1xx_rcc_ops = {
+ .read = stm32f1xx_rcc_read,
+ .write = stm32f1xx_rcc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f1xx_rcc = {
+ .name = TYPE_STM32F1XX_RCC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(rcc_cr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_cfgr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_cir, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_apb2rstr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_apb1rstr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_ahbenr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_apb2enr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_apb1enr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_bdcr, STM32F1XXRccState),
+ VMSTATE_UINT32(rcc_csr, STM32F1XXRccState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32f1xx_rcc_init(Object *obj)
+{
+ STM32F1XXRccState *s = STM32F1XX_RCC(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f1xx_rcc_ops, s,
+ TYPE_STM32F1XX_RCC, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f1xx_rcc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f1xx_rcc_reset;
+ dc->vmsd = &vmstate_stm32f1xx_rcc;
+}
+
+static const TypeInfo stm32f1xx_rcc_info = {
+ .name = TYPE_STM32F1XX_RCC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F1XXRccState),
+ .instance_init = stm32f1xx_rcc_init,
+ .class_init = stm32f1xx_rcc_class_init,
+};
+
+static void stm32f1xx_rcc_register_types(void)
+{
+ type_register_static(&stm32f1xx_rcc_info);
+}
+
+type_init(stm32f1xx_rcc_register_types)7.在include/hw/misc/创建stm32f1xx_rcc.h文件
diff --git a/include/hw/misc/stm32f1xx_rcc.h b/include/hw/misc/stm32f1xx_rcc.h
new file mode 100644
index 00000000..a9674766
--- /dev/null
+++ b/include/hw/misc/stm32f1xx_rcc.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2025 liang yan <[email protected]>
+ *
+ * STM32F1XX RCC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#ifndef STM32F1XX_RCC_H
+#define STM32F1XX_RCC_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+
+#define RCC_CR 0x00
+#define RCC_CFGR 0x04
+#define RCC_CIR 0x08
+#define RCC_APB2RSTR 0x0c
+#define RCC_APB1RSTR 0x10
+#define RCC_AHBENR 0x14
+#define RCC_APB2ENR 0x18
+#define RCC_APB1ENR 0x1c
+#define RCC_BDCR 0x20
+#define RCC_CSR 0x24
+
+#define RCC_CR_HSION (1<<0)
+#define RCC_CR_HSIRDY (1<<1)
+#define RCC_CR_HSENON (1<<16)
+#define RCC_CR_HSERDY (1<<17)
+#define RCC_CR_PLLON (1<<24)
+#define RCC_CR_PLLRDY (1<<25)
+
+#define RCC_CSR_LSION (1<<0)
+#define RCC_CSR_LSIRDY (1<<1)
+
+#define RCC_BDCR_LSEON (1<<0)
+#define RCC_BDCR_LSERDY (1<<1)
+#define RCC_CFGR_SW_HSI (0x00)
+#define RCC_CFGR_SW_HSE (0x01)
+#define RCC_CFGR_SW_PLL (0x02)
+#define RCC_CFGR_SW_MASK (0x03)
+#define RCC_CFGR_PLLXTPRE (1<<17)
+#define RCC_CFGR_PLL_SRC (1 << 16)
+
+#define RCC_CFGR_SWS_HSI (0x00 << 2)
+#define RCC_CFGR_SWS_HSE (0x01 << 2)
+#define RCC_CFGR_SWS_PLL (0x02 << 2)
+
+
+
+#define RCC_CFGR2_PREDIV1_MASK (0x0F)
+
+#define TYPE_STM32F1XX_RCC "stm32f1xx-rcc"
+#define STM32F1XX_RCC(obj) \
+ OBJECT_CHECK(STM32F1XXRccState, (obj), TYPE_STM32F1XX_RCC)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t rcc_cr;
+ uint32_t rcc_cfgr;
+ uint32_t rcc_cir;
+ uint32_t rcc_apb2rstr;
+ uint32_t rcc_apb1rstr;
+ uint32_t rcc_ahbenr;
+ uint32_t rcc_apb2enr;
+ uint32_t rcc_apb1enr;
+ uint32_t rcc_bdcr;
+ uint32_t rcc_csr;
+
+} STM32F1XXRccState;
+
+#endif总结
1、本文描述了如何在qemu中添加stm32f103平台上RCC控制器实现；
2、RCC模块主要功能就是配置STM32103运行时的时钟频率;
2、完成的提交记录，请查看代码库链接;
链接：
1、qemu代码库链接