- MCU(dsPIC33) SPI调试
a. MOSI output
/Data change at rising edge, and slave sample at falling edge

c
void InitSPI2(void)
{ // since sending only, no need for INTS.
FPGA_CS_N_OUT_LED16_En; //FPGA_CS# select
FPGA_CS_N_LED16_En = 1;//FPGA_CS# high
IFS2bits.SPI2IF = 0; //Clear the interrupt flag
IFS2bits.SPI2EIF = 0; //0-Dis Int, 1--En
SPI2CON1bits.DISSCK = 0;// 0-enable clk
SPI2CON1bits.DISSDO = 0;// 0-enable SDO
SPI2CON1bits.MODE16 = 0;// 1--16bits transfer.0--8 bit
SPI2CON1bits.SMP = 0; //0--sample during data; 1--sample end of data
//Data change at rising edge, and slave sample at falling edge
SPI2CON1bits.CKE = 1; //1--Data shift out at clk from work to idle
SPI2CON1bits.CKP = 1;// 1--CLK is 1 at idle state and clk is 0 at work
SPI2CON1bits.SSEN = 0; //0--Not use CS pin
SPI2CON1bits.MSTEN = 1; //1--Master mode
SPI2CON1bits.SPRE = 0x06;//b110--Sub clock 2:1 presale
SPI2CON1bits.PPRE = 0x10; //b10--main clock 4:1 prescale�� b01-16:1
SPI2BUF = 0x0000;
// SPI1CON1 = 0x057A; // 0000 0000 0111 1111
SPI2STATbits.SPIROV = 0; // Clear Overflow bit
SPI2STATbits.SPIEN = 1; // Enable the peripheral
IEC2bits.SPI2IE = 0; //0-- Dis SPI INT, 1-En
FPGA_CS_N_LED16_En = 0;//Enable FPGA CS#
}

**?现在问题,怎么MCU读取FPGA数据 Via MISO**
- FPGA调试
a: FPGA收到的数据是正确的 via MOSI, 通过FPGA Reveal analyzer抓取的数据。
b. 但是发送出的数据是错误的 via miso
发送8'h44, 现在FPGA代码是错误的
