xilinx xadc 例化

1、外部调用例化

wire $15:0$ xadc_channel_7 ;

wire $15:0$ xadc_channel_13 ;

wire $15:0$ xadc_channel_14 ;

wire Vp_Vn_0_v_p ;

wire Vp_Vn_0_v_n ;

wire Vaux7_0_v_n ;

wire Vaux7_0_v_p ;

wire Vaux13_0_v_n ;

wire Vaux13_0_v_p ;

wire Vaux14_0_v_n ;

wire Vaux14_0_v_p ;

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

xadc_top u_xadc(

/*input */ .DCLK (clk_80M ), // Clock input for DRP

/*input */ .RESET (!rst_n ),

// /*input */ .VP (Vp_Vn_0_v_p ),// Dedicated and Hardwired Analog Input Pair

// /*input */ .VN (Vp_Vn_0_v_n ),// Dedicated and Hardwired Analog Input Pair

// /*input $15:0$ */ .VAUXP ( {0,VAUXP1,0,VAUXP,0} ), // Auxiliary analog channel inputs

// /*input $15:0$ */ .VAUXN ( {0,VAUXN1,0,VAUXN,0} ), // Auxiliary analog channel inputs

/*input wire*/ .vp_in (Vp_Vn_0_v_p ),

/*input wire*/ .vn_in (Vp_Vn_0_v_n ),

/*input wire*/ .vauxp7 (Vaux7_0_v_n ),

/*input wire*/ .vauxn7 (Vaux7_0_v_p ),

/*input wire*/ .vauxp13 (Vaux13_0_v_n ),

/*input wire*/ .vauxn13 (Vaux13_0_v_p ),

/*input wire*/ .vauxp14 (Vaux14_0_v_n ),

/*input wire*/ .vauxn14 (Vaux14_0_v_p ),

/*output reg $15:0$ */ .xadc_channel7_o (xadc_channel_7 ), // $14:1$

/*output reg $15:0$ */ .xadc_channel13_o (xadc_channel_13 ), // $14:1$

/*output reg $15:0$ */ .xadc_channel14_o (xadc_channel_14 ) // $14:1$

);

assign Vaux7_0_v_n = F_Sensor_VCC3V3_10G_P ;

assign Vaux7_0_v_p = F_Sensor_VCC3V3_10G_N ;

assign Vaux13_0_v_n = F_Sensor_12V0_P ;

assign Vaux13_0_v_p = F_Sensor_12V0_N ;

assign Vaux14_0_v_n = F_Sensor_PWR3V3_100G_P;

assign Vaux14_0_v_p = F_Sensor_PWR3V3_100G_N;

// INST_TAG_END ------ End INSTANTIATION Template ---------

2、xadc IP例化

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

xadc_wiz_0 u_xadc_wiz_0 (

.di_in(di_drp), // input wire $15 : 0$ di_in

.daddr_in(daddr), // input wire $6 : 0$ daddr_in

.den_in(den_reg $0$ ), // input wire den_in

.dwe_in(dwe_reg $0$ ), // input wire dwe_in

.drdy_out(drdy), // output wire drdy_out

.do_out(do_drp), // output wire $15 : 0$ do_out

.dclk_in(dclk_bufg), // input wire dclk_in

.reset_in(RESET), // input wire reset_in

.vp_in(vp_in), // input wire vp_in

.vn_in(vn_in), // input wire vn_in

.vauxp7(vauxp7), // input wire vauxp7

.vauxn7(vauxn7), // input wire vauxn7

.vauxp13(vauxp13), // input wire vauxp13

.vauxn13(vauxn13), // input wire vauxn13

.vauxp14(vauxp14), // input wire vauxp14

.vauxn14(vauxn14), // input wire vauxn14

.channel_out(CHANNEL), // output wire $4 : 0$ channel_out

.eoc_out(eoc), // output wire eoc_out

.alarm_out(ALM), // output wire alarm_out

.eos_out(eos), // output wire eos_out

.busy_out(busy) // output wire busy_out

);

// INST_TAG_END ------ End INSTANTIATION Template ---------

3、原语例化

XADC #(// Initializing the XADC Control Registers

.INIT_40(16'h9000),// averaging of 16 selected for external channels

.INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration

.INIT_42(16'h0400),// Set DCLK divides

.INIT_48(16'h0000),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration

.INIT_49(16'h7efe),// CHSEL2 - enable aux analog channels 1 - 7,9 - 14

.INIT_4A(16'h0000),// SEQAVG1 disabled

.INIT_4B(16'h0000),// SEQAVG2 disabled

.INIT_4C(16'h0000),// SEQINMODE0

.INIT_4D(16'h0000),// SEQINMODE1

.INIT_4E(16'h0000),// SEQACQ0

.INIT_4F(16'h0000),// SEQACQ1

.INIT_50(16'hb5ed),// Temp upper alarm trigger 85掳C

.INIT_51(16'h5999),// Vccint upper alarm limit 1.05V

.INIT_52(16'hA147),// Vccaux upper alarm limit 1.89V

.INIT_53(16'hdddd),// OT upper alarm limit 125掳C - see Thermal Management

.INIT_54(16'ha93a),// Temp lower alarm reset 60掳C

.INIT_55(16'h5111),// Vccint lower alarm limit 0.95V

.INIT_56(16'h91Eb),// Vccaux lower alarm limit 1.71V

.INIT_57(16'hae4e),// OT lower alarm reset 70掳C - see Thermal Management

.INIT_58(16'h5999),// VCCBRAM upper alarm limit 1.05V

.SIM_MONITOR_FILE("design.txt")// Analog Stimulus file for simulation

)

XADC_INST (// Connect up instance IO. See UG480 for port descriptions

.CONVST (1'b0),// not used

.CONVSTCLK (1'b0), // not used

.DADDR (daddr),

.DCLK (dclk_bufg),

.DEN (den_reg $0$ ),

.DI (di_drp),

.DWE (dwe_reg $0$ ),

.RESET (RESET),

.VAUXN (vauxn_active ),

.VAUXP (vauxp_active ),

.ALM (ALM),

.BUSY (busy),

.CHANNEL(CHANNEL),

.DO (do_drp),

.DRDY (drdy),

.EOC (eoc),

.EOS (eos),

.JTAGBUSY (),// not used

.JTAGLOCKED (),// not used

.JTAGMODIFIED (),// not used

.OT (OT),

.MUXADDR (),// not used

.VP (VP),

.VN (VN)

);

assign vauxp_active = VAUXP $15:0$ ;

assign vauxn_active = VAUXN $15:0$ ;