[HDLBits] Fsm serialdp

See also: Serial receiver and datapath

We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.

Change your FSM and datapath to perform odd parity checking. Assert the done signal only if a byte is correctly received and its parity check passes. Like the serial receiver FSM, this FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

You are provided with the following module that can be used to calculate the parity of the input stream (It's a TFF with reset). The intended use is that it should be given the input bit stream, and reset at appropriate times so it counts the number of 1 bits in each byte.

复制代码
module parity (
    input clk,
    input reset,
    input in,
    output reg odd);

    always @(posedge clk)
        if (reset) odd <= 0;
        else if (in) odd <= ~odd;

endmodule

Note that the serial protocol sends the least significant bit first, and the parity bit after the 8 data bits.

复制代码
module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    reg [3:0] state,next;
    reg odd;
    //0:还没接到起始位,1:接到起始位,...,9:接到最后一个数据位,10:接到奇偶校验位,11:接到终止位,12:没接到终止位
    wire res;
    always@(*) begin
        case(state)
            0:next<=in?0:1;
            1:next<=2;
            2:next<=3;
            3:next<=4;
            4:next<=5;
            5:next<=6;
            6:next<=7;
            7:next<=8;
            8:next<=9;
            9:next<=10;
            10:next<=in?11:12;
            11:next<=in?0:1;
            //接到终止位后接到0即开始位,那就直接跳到1
            12:next<=in?0:12;
            //判断是否接到终止位。这里是设置了两种终止位状态来判断是否done
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state<=0;
        else
            state<=next;
    end
    
    parity p1(clk, res, in, odd);
        
    assign done=(state==11&&(!odd));
    // Use FSM from Fsm_serial
    always@(posedge clk) begin
        case(state)
            1:out_byte[0]<=in;
            2:out_byte[1]<=in;
            3:out_byte[2]<=in;
            4:out_byte[3]<=in;
            5:out_byte[4]<=in;
            6:out_byte[5]<=in;
            7:out_byte[6]<=in;
            8:out_byte[7]<=in; 
        endcase
    end

    always@(*) begin
        if(state==11||state==0)
            res<=1;
        else
            res<=0;
    end

endmodule
相关推荐
小眼睛FPGA1 小时前
【RK3568+PG2L50H开发板实验例程】Linux部分/FPGA dma_memcpy_demo 读写案例
linux·运维·科技·ai·fpga开发·gpu算力
幸运学者2 小时前
xilinx axi datamover IP使用demo
fpga开发
搬砖的小码农_Sky3 小时前
XILINX Zynq-7000系列FPGA的架构
fpga开发·架构
热爱学习地派大星11 小时前
FPGA矩阵算法实现
fpga开发
热爱学习地派大星14 小时前
Xilinx FPGA功耗评估
fpga开发·verilog·vivado·fpga功耗·xpe
搬砖的小码农_Sky19 小时前
XILINX Ultrascale+ Kintex系列FPGA的架构
fpga开发·架构
XvnNing20 小时前
【Verilog硬件语言学习笔记4】FPGA串口通信
笔记·学习·fpga开发
进击的奶龙20 小时前
21verilog函数
verilog·基础语法
千宇宙航20 小时前
闲庭信步使用SV搭建图像测试平台:第二十七课——图像的腐蚀
图像处理·计算机视觉·fpga开发
尤老师FPGA11 天前
使用DDR4控制器实现多通道数据读写(十六)
fpga开发·ddr4