有符号数乘有符号数乘法器 verilog+ testbench 代码
ssmultiplier.v
c
module ssmultiplier #(
parameter NUMBER1 = 8 ,
parameter NUMBER2 = 8
)(
input signed [NUMBER1-1 : 0] input1 ,
input signed [NUMBER2-1 : 0] input2 ,
input clk ,
input rst_n ,
input begin_en ,
output reg finish_en ,
output reg [NUMBER1+NUMBER2-2 : 0] out
);
//======================================================================================\
// define parameter and internal signal \
//======================================================================================\
reg [NUMBER1+NUMBER2-2 : 0] out1 ;
//==========================================================================================\
// next is main code \\
//===========================================================================================\\
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 0)
begin
out <= 0 ;
end
else if(begin_en && finish_en )
begin
out[NUMBER1+NUMBER2-3:0] <= input1[NUMBER1-2:0] * input2[NUMBER2-2 : 0] ;
out[NUMBER1+NUMBER2-2] <= (~input2[NUMBER2-1]&&input1[NUMBER1-1]) || (input2[NUMBER2-1]&&~input1[NUMBER1-1]) ;
end
else
out <= out ;
end
always@(posedge clk or negedge rst_n )
begin
if(rst_n == 0)
begin
out1 <= 0 ;
end
else
out1 <= out ;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 0)
begin
finish_en <= 1'b1 ;
end
else if(out != out1)
begin
finish_en <= 1'b1 ;
end
else
finish_en <= 1'b0 ;
end
endmodule
ssmultiplier_tb.v
c
module ssmultiplier_tb #(
parameter NUMBER1 = 4 ,
parameter NUMBER2 = 4
);
reg [NUMBER1-1 : 0] input1 ;
reg [NUMBER2-1 : 0] input2 ;
reg clk ;
reg rst_n ;
reg begin_en ;
wire finish_en ;
wire [(NUMBER1)+(NUMBER2)-2 : 0] out ;
ssmultiplier#(
.NUMBER1 ( NUMBER1 ),
.NUMBER2 ( NUMBER2 )
)u_ssmultiplier(
.input1 ( input1 ),
.input2 ( input2 ),
.clk ( clk ),
.rst_n ( rst_n ),
.begin_en ( begin_en ),
.finish_en ( finish_en ),
.out ( out )
);
always #5 clk = ~clk ;
initial begin
clk = 0 ;
rst_n = 0 ;
input1 = 2'b00 ;
input2 = 2'b00 ;
begin_en = 1 ;
#20
rst_n = 1 ;
input1 = 4'b0001 ;
input2 = 4'b1100 ;
#20
input1 = 4'b1010;
input2 = 4'b1111 ;
#20
input1 = 4'b0011 ;
input2 = 4'b1100 ;
#20
input1 = 4'b1100 ;
input2 = 4'b0100 ;
end
endmodule