spinalhdl，vivado，fpga

https://spinalhdl.github.io/SpinalDoc-RTD/master

spinal hdl

sudo apt install openjdk-17-jdk scala curl

echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list

echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list

curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get\&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add

sudo apt update

sudo apt install sbt

vscode 安装"Scala (Metals)"扩展，将官方的示例放到 vscode 里，然后等右下角弹框，选 sbt，下一个选 import build，等待完成，然后打开 hw/spinal/projectname/MyTopLevel.scala，"object MyTopLevelVerilog extends App"上面会出现"run | debug"，点击 run，就会在 hw/gen 下生成 .v 文件

生成波形文件和查看波形

sudo apt install zlib1g-dev

sudo apt install verilator gtkwave

这也会生成 .v 文件，在 tmp/job_1 里，如果测试代码完整可以直接走这步

打开 hw/spinal/projectname/MyTopLevelSim.scala，"object MyTopLevelSim extends App"上面也会出现"run | debug"，点击 run，就会在 simWorkspace/MyTopLevel 下生成 .fst 波形文件，可以使用 gtkwave simWorkspace/MyTopLevel/*.fst 直接打开查看波形

vivado

安装选项选择 vivado，vivado ml enterprise，其他默认，等待下载安装完成，默认安装到 /tools/Xilinx

如果无法使用 jtag 调试器，就需要升级 linux 内核，先 apt update & apt upgrade -y 升级一次，如果不行就使用测试通道。

测试通道：包名是 linux-image-amd64。使用"apt search linux-image-amd64"查看仓库里的版本，但是版本不一定够，可以修改"/etc/apt/sources.list"文件里的系统代号为"testing"并apt update，再apt install linux-image-amd64，然后重启，查看内核版本，弄好了就可以把"/etc/apt/sources.list"文件内容还原。

安装:

二选一
.bin 在线安装器直接安装
    chmod a+x ./Xilinx_Unified_2023.1_0507_1903_Lin64.bin
    sudo ./Xilinx_Unified_2023.1_0507_1903_Lin64.bin

.tar...，在线安装器下载压缩包解压安装
    tar -xvf Xilinx...tar...
    cd Xilinx...
    sudo ./xsetup

安装调试器 .rules file:

cd /tools/Xilinx/Vivado/2023.1/data/xicom/cable_drivers/lin64/install_script/install_drivers
sudo ./install_drivers

启动:

默认安装到 /tools/Xilinx/。由于是 sudo 安装，桌面图标在 /root/Desktop/ 下，需要 sudo cp /root/Desktop/* /usr/share/applications/

命令行启动：/tools/Xilinx/Vivado/2023.1/bin/vivado

或桌面图标启动

报错及问题

从命令行启动才能看到报错信息

报错
    /tools/Xilinx/Vivado/2023.1/bin/rdiArgs.sh: 行 37: 警告：setlocale: LC_ALL: 无法改变区域设置 (en_US.UTF-8)：没有那个文件或目录...
    /bin/bash: warning: setlocale: LC_ALL: cannot change locale (en_US.UTF-8)...
解决方法
    sudo localedef -i en_US -f UTF-8 en_US.UTF-8

报错或点击 vivado 图标无法启动
    application-specific initialization failed: couldn't load file "librdi_commontasks.so": libtinfo.so.5: cannot open shared object file: No such file or directory..
解决方法
    sudo ln /usr/lib/x86_64-linux-gnu/libtinfo.so.6 /usr/lib/x86_64-linux-gnu/libtinfo.so.5

一个 led 闪烁的示例（MyTopLevel.scala）

package projectname

import spinal.core._

// Hardware definition
case class MyTopLevel() extends Component {
  val io = new Bundle {
    val led = out Bool ()
  }

  val counter = Reg(UInt(32 bits))
  val led = Reg(Bool ())
  
  io.led := led

  // 每秒反转 led
  // reality 是 frequency_t 枚举类型里的值。仿真用低频 simulation 值，板卡测试用实际频率
  when(counter <= frequency_t.reality.asBits.asUInt) {
    counter := counter + 1
  } otherwise {
    counter := 0
    led := !led
  }
}

// 自定义的枚举类型
object frequency_t extends SpinalEnum{
  val simulation, reality = newElement()
  
  defaultEncoding = SpinalEnumEncoding("staticEncoding")(
    simulation -> 10,
    reality -> 100000000 // 100M
  )
}

object MyTopLevelVerilog extends App {
  Config.spinal.generateVerilog(MyTopLevel())
}

其生成的 veriloghdl（MyTopLevel.v）

// Generator : SpinalHDL v1.8.1    git head : 2a7592004363e5b40ec43e1f122ed8641cd8965b
// Component : MyTopLevel

`timescale 1ns/1ps

module MyTopLevel (
  output              io_led,
  input               clk,
  input               reset
);
  localparam frequency_t_simulation = 27'd10;
  localparam frequency_t_reality = 27'd100000000;

  wire       [31:0]   _zz_when_MyTopLevel_l16;
  wire       [26:0]   _zz_when_MyTopLevel_l16_1;
  reg        [31:0]   counter;
  reg                 led;
  wire                when_MyTopLevel_l16;

  assign _zz_when_MyTopLevel_l16_1 = frequency_t_reality;
  assign _zz_when_MyTopLevel_l16 = {5'd0, _zz_when_MyTopLevel_l16_1};
  assign io_led = led;
  assign when_MyTopLevel_l16 = (counter <= _zz_when_MyTopLevel_l16);
  always @(posedge clk) begin
    if(when_MyTopLevel_l16) begin
      counter <= (counter + 32'h00000001);
    end else begin
      counter <= 32'h0;
      led <= (! led);
    end
  end


endmodule

其仿真（MyTopLevelSim.scala）

led 只要输出，所以其他的去掉了

package projectname

import spinal.core._
import spinal.core.sim._

object MyTopLevelSim extends App {
  Config.sim.compile(MyTopLevel()).doSim { dut =>
    // Fork a process to generate the reset and the clock on the dut
    dut.clockDomain.forkStimulus(period = 10)

    for (idx <- 0 to 99) { // 仿真运行 100 个时钟

      // Wait a rising edge on the clock
      dut.clockDomain.waitRisingEdge()
    }
  }
}
​```