[HDLBits] Tb/clock

You are provided a module with the following declaration:

module dut ( input clk ) ;

Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.

051015202530354045...

`timescale 1ps/1ps

//注意仿真单位ps
module top_module ( );
	parameter clk_period = 10;  
	reg clk;  
	initial
    	clk = 0;  
	always #(clk_period/2) clk = ~clk;  

    dut instance1(clk);
endmodule