vivado Miscellaneous Net-Related Constraints

Miscellaneous Net-Related Constraints
KEEP
Applied To
Nets
Constraint Values
• TRUE
• FALSE
UCF Example
net x_int KEEP = TRUE;
XDC Example
set_property DONT_TOUCH true get_nets x_int
SAVE NET FLAG
Applied To
Nets
Constraint Values
N/A
UCF Example
net x_int S;
XDC Example
set_property DONT_TOUCH true get_nets x_int
LOCK_PINS
Applied To
LUT cell
Constraint Values
CSV string: I0-5:A6-1
UCF Example
INST LUT1 LOCK_PINS = I3:A6, I2:A5;
XDC Example
set_property LOCK_PINS {I3:A6 I2:A5} get_cells LUT1
ROUTE
Applied To
Nets
Constraint Values
Directed Routing String (DIRT)
UCF Example
NET n85 ROUTE={2;1;-4!-1;-53320; . . .16;-8!};
XDC Example
set_property FIXED_ROUTE {EE2BEG0 NR1BEG0\ CLBLL_LL_AX} get_nets n85
Note : ISE Design Suite directed routing strings and Vivado Design Suite net route
properties are incompatible. Vivado uses a unique, un-encoded format
Configuration-Related Constraints
CONFIG PROHIBIT
Pin site
Applied To
Sites
Constraint Values
Pin site
UCF Example
CONFIG PROHIBIT = K24, K26, K27, K28;
XDC Example
set_property PROHIBIT true get_sites {K24 K26 K27 K28}
Bank number
Applied To
Sites
Constraint Values
Bank number
UCF Example
CONFIG PROHIBIT = BANK34, BANK35, BANK36;
XDC Example
set_property PROHIBIT true get_sites -of \[get_iobanks 34\\ 35 36]
RAM(1)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB18_X0Y0;
XDC Example
set_property PROHIBIT true get_sites RAMB18_X0Y0
RAM(2)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB18_X0Y1, RAMB18_X0Y3, RAMB18_X0Y5;
XDC Example
set_property PROHIBIT true get_sites {RAMB18_X0Y1\\RAMB18_X0Y3 RAMB18_X0Y5}
Note : The comma-separated list shown here uses RAM sites but can use any supported
site type.
RAM(3)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB36_X1Y1:RAMB36_X2Y2;
XDC Example
set_property PROHIBIT true get_sites -range {RAMB36_X1Y1\\ RAMB36_X2Y2}
RAM(4)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB36_X3Y*;
XDC Example
set_property PROHIBIT true get_sites RAMB36_X3Y\*
DSP48
Applied To
Sites
Constraint Values
DSP48s
UCF Example
CONFIG PROHIBIT = DSP48_X0Y*;
XDC Example
set_property PROHIBIT true get_sites DSP48_X0Y\*
SLICE
Applied To
Sites
Constraint Values
Slices
UCF Example
CONFIG PROHIBIT = SLICE_X0Y0:SLICE_X47Y49;
XDC Example
set_property PROHIBIT true get_sites -range {SLICE_X0Y0\\ SLICE_X47Y49}
ILOGIC
Applied To
Sites
Constraint Values
ILOGIC
UCF Example
CONFIG PROHIBIT = ILOGIC_X0Y0:ILOGIC_X0Y49;
XDC Example
set_property PROHIBIT true get_sites -range {ILOGIC_X0Y0\\ ILOGIC_X0Y49}
OLOGIC
Applied To
Sites
Constraint Values
OLOGIC
UCF Example
CONFIG PROHIBIT = OLOGIC_X0Y0:OLOGIC_X0Y49;
XDC Example
set_property PROHIBIT true get_sites -range {OLOGIC_X0Y0\\ OLOGIC_X0Y49}
BUFGCTRL
Applied To
Sites
Constraint Values
BUFGCTRL
UCF Example
CONFIG PROHIBIT = BUFGCTRL_X0Y0:BUFGCTRL_X0Y15;
XDC Example
set_property PROHIBIT true get_sites -range\\ {BUFGCTRL_X0Y0 BUFGCTRL_X0Y15}
BUFR
Applied To
Sites
Constraint Values
BUFR
UCF Example
CONFIG PROHIBIT = BUFR_X0Y0:BUFR_X0Y3;
XDC Example
set_property PROHIBIT true get_sites -range {BUFR_X0Y0\\ BUFR_X0Y3}
BUFIO
Applied To
Sites
Constraint Values
BUFIO
UCF Example
CONFIG PROHIBIT = BUFIO_X0Y0:BUFIO_X0Y3;
XDC Example
set_property PROHIBIT true get_sites -range {BUFIO_X0Y0\\ BUFIO_X0Y3}
BUFHCE
Applied To
Sites
Constraint Values
BUFHCE
UCF Example
CONFIG PROHIBIT = BUFHCE_X0Y0:BUFHCE_X1Y11;
XDC Example
set_property PROHIBIT true get_sites -range {BUFHCE_X0Y0\\ BUFHCE_X1Y11}
Voltage
Applied To
I/O bank
Constraint Values
Voltage
UCF Example
CONFIG INTERNAL_VREF_BANK14 = 0.75;
XDC Example
set_property INTERNAL_VREF 0.75 get_iobanks 14
NONE
Applied To
I/O bank
Constraint Values
NONE
UCF Example
CONFIG INTERNAL_VREF_BANK0 = NONE;
XDC Example
reset_property INTERNAL_VREF get_iobanks 0
CONFIG DCI_CASCADE
Applied To
I/O banks
Constraint Values
Bank sequence
UCF Example
CONFIG DCI_CASCADE = 17 15 14;
XDC Example
set_property DCI_CASCADE {15 14} get_iobanks 17

相关推荐
tju新生代魔迷4 小时前
Verilog HDL 学习笔记(十)| 第10章 时序和延迟
笔记·学习·fpga开发
aprilaaaaa9 小时前
(TC397 学习笔记)二、ICU和TIM的时钟计算
笔记·学习·fpga开发
X_xcccc12 小时前
2026高端FPGA开发平台权威评测与选型指南
fpga开发
威嵌神州12 小时前
军工加固计算机七大核心特性解析|国产化、宽温、强加固工程实现
嵌入式硬件·计算机网络·fpga开发
FPGA小迷弟12 小时前
高云半导体深度解读:国产FPGA车规赛道的领跑者
fpga开发
努力搬砖的小H13 小时前
FPGA应用技巧之Block Design基本使用方法
功能测试·fpga开发·zynq·block design
ALINX技术博客13 小时前
【黑金云课堂】FPGA技术教程FPGA 基础:HDMI视频输入与环路输出实验
fpga开发·音视频
hahaha601614 小时前
HLS高层次综合设计--axi之burst纠偏
开发语言·算法·fpga开发·c#
珞光电子USRP SDR软件无线电平台1 天前
国产嵌入式SDR平台LW-E320-G详解:射频、FPGA、ARM架构与应用选型
arm开发·fpga开发·架构
FPGA小迷弟1 天前
【硬核通俗】FPGA实现SDR软件无线电完整技术解析(原理+架构+实战)
fpga开发·dsp开发·sdr·无线电