Miscellaneous Net-Related Constraints
KEEP
Applied To
Nets
Constraint Values
• TRUE
• FALSE
UCF Example
net x_int KEEP = TRUE;
XDC Example
set_property DONT_TOUCH true [get_nets x_int]
SAVE NET FLAG
Applied To
Nets
Constraint Values
N/A
UCF Example
net x_int S;
XDC Example
set_property DONT_TOUCH true [get_nets x_int]
LOCK_PINS
Applied To
LUT cell
Constraint Values
CSV string: I[0-5]:A[6-1]
UCF Example
INST LUT1 LOCK_PINS = I3:A6, I2:A5;
XDC Example
set_property LOCK_PINS {I3:A6 I2:A5} [get_cells LUT1]
ROUTE
Applied To
Nets
Constraint Values
Directed Routing String (DIRT)
UCF Example
NET n85 ROUTE={2;1;-4!-1;-53320; . . .16;-8!};
XDC Example
set_property FIXED_ROUTE {EE2BEG0 NR1BEG0\ CLBLL_LL_AX} [get_nets
n85]
Note : ISE Design Suite directed routing strings and Vivado Design Suite net route
properties are incompatible. Vivado uses a unique, un-encoded format
Configuration-Related Constraints
CONFIG PROHIBIT
Pin site
Applied To
Sites
Constraint Values
Pin site
UCF Example
CONFIG PROHIBIT = K24, K26, K27, K28;
XDC Example
set_property PROHIBIT true [get_sites {K24 K26 K27 K28}]
Bank number
Applied To
Sites
Constraint Values
Bank number
UCF Example
CONFIG PROHIBIT = BANK34, BANK35, BANK36;
XDC Example
set_property PROHIBIT true [get_sites -of [get_iobanks 34\ 35 36]]
RAM(1)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB18_X0Y0;
XDC Example
set_property PROHIBIT true [get_sites RAMB18_X0Y0]
RAM(2)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB18_X0Y1, RAMB18_X0Y3, RAMB18_X0Y5;
XDC Example
set_property PROHIBIT true [get_sites {RAMB18_X0Y1\RAMB18_X0Y3
RAMB18_X0Y5}]
Note : The comma-separated list shown here uses RAM sites but can use any supported
site type.
RAM(3)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB36_X1Y1:RAMB36_X2Y2;
XDC Example
set_property PROHIBIT true [get_sites -range {RAMB36_X1Y1\
RAMB36_X2Y2}]
RAM(4)
Applied To
Sites
Constraint Values
RAMs
UCF Example
CONFIG PROHIBIT = RAMB36_X3Y*;
XDC Example
set_property PROHIBIT true [get_sites RAMB36_X3Y*]
DSP48
Applied To
Sites
Constraint Values
DSP48s
UCF Example
CONFIG PROHIBIT = DSP48_X0Y*;
XDC Example
set_property PROHIBIT true [get_sites DSP48_X0Y*]
SLICE
Applied To
Sites
Constraint Values
Slices
UCF Example
CONFIG PROHIBIT = SLICE_X0Y0:SLICE_X47Y49;
XDC Example
set_property PROHIBIT true [get_sites -range {SLICE_X0Y0\
SLICE_X47Y49}]
ILOGIC
Applied To
Sites
Constraint Values
ILOGIC
UCF Example
CONFIG PROHIBIT = ILOGIC_X0Y0:ILOGIC_X0Y49;
XDC Example
set_property PROHIBIT true [get_sites -range {ILOGIC_X0Y0\
ILOGIC_X0Y49}]
OLOGIC
Applied To
Sites
Constraint Values
OLOGIC
UCF Example
CONFIG PROHIBIT = OLOGIC_X0Y0:OLOGIC_X0Y49;
XDC Example
set_property PROHIBIT true [get_sites -range {OLOGIC_X0Y0\
OLOGIC_X0Y49}]
BUFGCTRL
Applied To
Sites
Constraint Values
BUFGCTRL
UCF Example
CONFIG PROHIBIT = BUFGCTRL_X0Y0:BUFGCTRL_X0Y15;
XDC Example
set_property PROHIBIT true [get_sites -range\ {BUFGCTRL_X0Y0
BUFGCTRL_X0Y15}]
BUFR
Applied To
Sites
Constraint Values
BUFR
UCF Example
CONFIG PROHIBIT = BUFR_X0Y0:BUFR_X0Y3;
XDC Example
set_property PROHIBIT true [get_sites -range {BUFR_X0Y0\
BUFR_X0Y3}]
BUFIO
Applied To
Sites
Constraint Values
BUFIO
UCF Example
CONFIG PROHIBIT = BUFIO_X0Y0:BUFIO_X0Y3;
XDC Example
set_property PROHIBIT true [get_sites -range {BUFIO_X0Y0\
BUFIO_X0Y3}]
BUFHCE
Applied To
Sites
Constraint Values
BUFHCE
UCF Example
CONFIG PROHIBIT = BUFHCE_X0Y0:BUFHCE_X1Y11;
XDC Example
set_property PROHIBIT true [get_sites -range {BUFHCE_X0Y0\
BUFHCE_X1Y11}]
Voltage
Applied To
I/O bank
Constraint Values
Voltage
UCF Example
CONFIG INTERNAL_VREF_BANK14 = 0.75;
XDC Example
set_property INTERNAL_VREF 0.75 [get_iobanks 14]
NONE
Applied To
I/O bank
Constraint Values
NONE
UCF Example
CONFIG INTERNAL_VREF_BANK0 = NONE;
XDC Example
reset_property INTERNAL_VREF [get_iobanks 0]
CONFIG DCI_CASCADE
Applied To
I/O banks
Constraint Values
Bank sequence
UCF Example
CONFIG DCI_CASCADE = 17 15 14;
XDC Example
set_property DCI_CASCADE {15 14} [get_iobanks 17]
vivado Miscellaneous Net-Related Constraints
cckkppll2024-05-25 1:08
相关推荐
XINVRY-FPGA3 小时前
EPM240T100I5N Altera FPGA MAX II CPLD第二层皮-合肥8 小时前
FPGA实现ETH接口璞致电子11 小时前
【PZ-ZU47DR-KFB】璞致FPGA ZYNQ UltraScalePlus RFSOC QSPI Flash 固化常见问题说明陌夏微秋12 小时前
FPGA硬件设计2 最小芯片系统-ZYNQ7020/7010风已经起了1 天前
FPGA学习笔记——IIC协议简介逐梦之程1 天前
FPGA-Vivado2017.4-建立AXI4用于单片机与FPGA之间数据互通XINVRY-FPGA2 天前
10CL016YF484C8G Altera FPGA Cyclone嵌入式-老费2 天前
产品开发实践(常见的软硬结合方式)FakeOccupational3 天前
【电路笔记 通信】AXI4-Lite协议 FPGA实现 & Valid-Ready Handshake 握手协议I'm a winner3 天前
FPGA+护理:跨学科发展的探索(五)