使用DDR4控制器实现多通道数据读写(十六)

一、概述

在之前的章节中讲述了ddr4的写模块和读模块接口信号和模块功能及时序分析，接下来继续沿着思路向下讲解，在之前的章节中给出了测试模块，和interconnect RTL IP核和DDR4 IP核的例化模版，也给出了ddr4的读写模块讲解。在本章节我们来把上述模块和IP使用信号连接，组成一个测试工程。

二、工程模块框架

在之前章节中，我们已经给出了测试模块（chnl_test）、ddr4写模块（ddr4_axi_wr_ctrl）、ddr4读模块（ddr4_axi_rd_ctrl）的接口信号，因为要创建4个通道的读写功能，所以需要将ddr4的读写模块例化4组，将每一组的接口信号连接到对应测试模块和对应的interconnect的axi4从端口。

三、Interconnect RTL IP例化接口信号

axi_interconnect_0 axi_interconnect_0 (

.INTERCONNECT_ACLK(c0_ddr4_clk), // input wire INTERCONNECT_ACLK

.INTERCONNECT_ARESETN(~c0_ddr4_rst), // | ~(c0_init_calib_complete)), // input wire INTERCONNECT_ARESETN

//chnl 0

.S00_AXI_ARESET_OUT_N(S00_AXI_ARESET_OUT_N), // output wire S00_AXI_ARESET_OUT_N

.S00_AXI_ACLK(clk_75m), // input wire S00_AXI_ACLK

.S00_AXI_AWID(S00_AXI_AWID), // input wire $3 : 0$ S00_AXI_AWID

.S00_AXI_AWADDR(S00_AXI_AWADDR), // input wire $31 : 0$ S00_AXI_AWADDR

.S00_AXI_AWLEN(S00_AXI_AWLEN), // input wire $7 : 0$ S00_AXI_AWLEN

.S00_AXI_AWSIZE(S00_AXI_AWSIZE), // input wire $2 : 0$ S00_AXI_AWSIZE

.S00_AXI_AWBURST(S00_AXI_AWBURST), // input wire $1 : 0$ S00_AXI_AWBURST

.S00_AXI_AWLOCK(S00_AXI_AWLOCK), // input wire S00_AXI_AWLOCK

.S00_AXI_AWCACHE(S00_AXI_AWCACHE), // input wire $3 : 0$ S00_AXI_AWCACHE

.S00_AXI_AWPROT(S00_AXI_AWPROT), // input wire $2 : 0$ S00_AXI_AWPROT

.S00_AXI_AWQOS(S00_AXI_AWQOS), // input wire $3 : 0$ S00_AXI_AWQOS

.S00_AXI_AWVALID(S00_AXI_AWVALID), // input wire S00_AXI_AWVALID

.S00_AXI_AWREADY(S00_AXI_AWREADY), // output wire S00_AXI_AWREADY

.S00_AXI_WDATA(S00_AXI_WDATA), // input wire $511 : 0$ S00_AXI_WDATA

.S00_AXI_WSTRB(S00_AXI_WSTRB), // input wire $63 : 0$ S00_AXI_WSTRB

.S00_AXI_WLAST(S00_AXI_WLAST), // input wire S00_AXI_WLAST

.S00_AXI_WVALID(S00_AXI_WVALID), // input wire S00_AXI_WVALID

.S00_AXI_WREADY(S00_AXI_WREADY), // output wire S00_AXI_WREADY

.S00_AXI_BID(S00_AXI_BID), // output wire $3 : 0$ S00_AXI_BID

.S00_AXI_BRESP(S00_AXI_BRESP), // output wire $1 : 0$ S00_AXI_BRESP

.S00_AXI_BVALID(S00_AXI_BVALID), // output wire S00_AXI_BVALID

.S00_AXI_BREADY(S00_AXI_BREADY), // input wire S00_AXI_BREADY

.S00_AXI_ARID(S00_AXI_ARID), // input wire $3 : 0$ S00_AXI_ARID

.S00_AXI_ARADDR(S00_AXI_ARADDR), // input wire $31 : 0$ S00_AXI_ARADDR

.S00_AXI_ARLEN(S00_AXI_ARLEN), // input wire $7 : 0$ S00_AXI_ARLEN

.S00_AXI_ARSIZE(S00_AXI_ARSIZE), // input wire $2 : 0$ S00_AXI_ARSIZE

.S00_AXI_ARBURST(S00_AXI_ARBURST), // input wire $1 : 0$ S00_AXI_ARBURST

.S00_AXI_ARLOCK(S00_AXI_ARLOCK), // input wire S00_AXI_ARLOCK

.S00_AXI_ARCACHE(S00_AXI_ARCACHE), // input wire $3 : 0$ S00_AXI_ARCACHE

.S00_AXI_ARPROT(S00_AXI_ARPROT), // input wire $2 : 0$ S00_AXI_ARPROT

.S00_AXI_ARQOS(S00_AXI_ARQOS), // input wire $3 : 0$ S00_AXI_ARQOS

.S00_AXI_ARVALID(S00_AXI_ARVALID), // input wire S00_AXI_ARVALID

.S00_AXI_ARREADY(S00_AXI_ARREADY), // output wire S00_AXI_ARREADY

.S00_AXI_RID(S00_AXI_RID), // output wire $3 : 0$ S00_AXI_RID

.S00_AXI_RDATA(S00_AXI_RDATA), // output wire $511 : 0$ S00_AXI_RDATA

.S00_AXI_RRESP(S00_AXI_RRESP), // output wire $1 : 0$ S00_AXI_RRESP

.S00_AXI_RLAST(S00_AXI_RLAST), // output wire S00_AXI_RLAST

.S00_AXI_RVALID(S00_AXI_RVALID), // output wire S00_AXI_RVALID

.S00_AXI_RREADY(S00_AXI_RREADY), // input wire S00_AXI_RREADY

//chnl 1

.S01_AXI_ARESET_OUT_N(S01_AXI_ARESET_OUT_N), // output wire S01_AXI_ARESET_OUT_N

.S01_AXI_ACLK(clk_125m), // input wire S01_AXI_ACLK

.S01_AXI_AWID(S01_AXI_AWID), // input wire $3 : 0$ S01_AXI_AWID

.S01_AXI_AWADDR(S01_AXI_AWADDR), // input wire $31 : 0$ S01_AXI_AWADDR

.S01_AXI_AWLEN(S01_AXI_AWLEN), // input wire $7 : 0$ S01_AXI_AWLEN

.S01_AXI_AWSIZE(S01_AXI_AWSIZE), // input wire $2 : 0$ S01_AXI_AWSIZE

.S01_AXI_AWBURST(S01_AXI_AWBURST), // input wire $1 : 0$ S01_AXI_AWBURST

.S01_AXI_AWLOCK(S01_AXI_AWLOCK), // input wire S01_AXI_AWLOCK

.S01_AXI_AWCACHE(S01_AXI_AWCACHE), // input wire $3 : 0$ S01_AXI_AWCACHE

.S01_AXI_AWPROT(S01_AXI_AWPROT), // input wire $2 : 0$ S01_AXI_AWPROT

.S01_AXI_AWQOS(S01_AXI_AWQOS), // input wire $3 : 0$ S01_AXI_AWQOS

.S01_AXI_AWVALID(S01_AXI_AWVALID), // input wire S01_AXI_AWVALID

.S01_AXI_AWREADY(S01_AXI_AWREADY), // output wire S01_AXI_AWREADY

.S01_AXI_WDATA(S01_AXI_WDATA), // input wire $511 : 0$ S01_AXI_WDATA

.S01_AXI_WSTRB(S01_AXI_WSTRB), // input wire $63 : 0$ S01_AXI_WSTRB

.S01_AXI_WLAST(S01_AXI_WLAST), // input wire S01_AXI_WLAST

.S01_AXI_WVALID(S01_AXI_WVALID), // input wire S01_AXI_WVALID

.S01_AXI_WREADY(S01_AXI_WREADY), // output wire S01_AXI_WREADY

.S01_AXI_BID(S01_AXI_BID), // output wire $3 : 0$ S01_AXI_BID

.S01_AXI_BRESP(S01_AXI_BRESP), // output wire $1 : 0$ S01_AXI_BRESP

.S01_AXI_BVALID(S01_AXI_BVALID), // output wire S01_AXI_BVALID

.S01_AXI_BREADY(S01_AXI_BREADY), // input wire S01_AXI_BREADY

.S01_AXI_ARID(S01_AXI_ARID), // input wire $3 : 0$ S01_AXI_ARID

.S01_AXI_ARADDR(S01_AXI_ARADDR), // input wire $31 : 0$ S01_AXI_ARADDR

.S01_AXI_ARLEN(S01_AXI_ARLEN), // input wire $7 : 0$ S01_AXI_ARLEN

.S01_AXI_ARSIZE(S01_AXI_ARSIZE), // input wire $2 : 0$ S01_AXI_ARSIZE

.S01_AXI_ARBURST(S01_AXI_ARBURST), // input wire $1 : 0$ S01_AXI_ARBURST

.S01_AXI_ARLOCK(S01_AXI_ARLOCK), // input wire S01_AXI_ARLOCK

.S01_AXI_ARCACHE(S01_AXI_ARCACHE), // input wire $3 : 0$ S01_AXI_ARCACHE

.S01_AXI_ARPROT(S01_AXI_ARPROT), // input wire $2 : 0$ S01_AXI_ARPROT

.S01_AXI_ARQOS(S01_AXI_ARQOS), // input wire $3 : 0$ S01_AXI_ARQOS

.S01_AXI_ARVALID(S01_AXI_ARVALID), // input wire S01_AXI_ARVALID

.S01_AXI_ARREADY(S01_AXI_ARREADY), // output wire S01_AXI_ARREADY

.S01_AXI_RID(S01_AXI_RID), // output wire $3 : 0$ S01_AXI_RID

.S01_AXI_RDATA(S01_AXI_RDATA), // output wire $511 : 0$ S01_AXI_RDATA

.S01_AXI_RRESP(S01_AXI_RRESP), // output wire $1 : 0$ S01_AXI_RRESP

.S01_AXI_RLAST(S01_AXI_RLAST), // output wire S01_AXI_RLAST

.S01_AXI_RVALID(S01_AXI_RVALID), // output wire S01_AXI_RVALID

.S01_AXI_RREADY(S01_AXI_RREADY), // input wire S01_AXI_RREADY

//chnl 2

.S02_AXI_ARESET_OUT_N(S02_AXI_ARESET_OUT_N), // output wire S02_AXI_ARESET_OUT_N

.S02_AXI_ACLK(clk_75m), // input wire S02_AXI_ACLK

.S02_AXI_AWID(S02_AXI_AWID), // input wire $3 : 0$ S02_AXI_AWID

.S02_AXI_AWADDR(S02_AXI_AWADDR), // input wire $31 : 0$ S02_AXI_AWADDR

.S02_AXI_AWLEN(S02_AXI_AWLEN), // input wire $7 : 0$ S02_AXI_AWLEN

.S02_AXI_AWSIZE(S02_AXI_AWSIZE), // input wire $2 : 0$ S02_AXI_AWSIZE

.S02_AXI_AWBURST(S02_AXI_AWBURST), // input wire $1 : 0$ S02_AXI_AWBURST

.S02_AXI_AWLOCK(S02_AXI_AWLOCK), // input wire S02_AXI_AWLOCK

.S02_AXI_AWCACHE(S02_AXI_AWCACHE), // input wire $3 : 0$ S02_AXI_AWCACHE

.S02_AXI_AWPROT(S02_AXI_AWPROT), // input wire $2 : 0$ S02_AXI_AWPROT

.S02_AXI_AWQOS(S02_AXI_AWQOS), // input wire $3 : 0$ S02_AXI_AWQOS

.S02_AXI_AWVALID(S02_AXI_AWVALID), // input wire S02_AXI_AWVALID

.S02_AXI_AWREADY(S02_AXI_AWREADY), // output wire S02_AXI_AWREADY

.S02_AXI_WDATA(S02_AXI_WDATA), // input wire $511 : 0$ S02_AXI_WDATA

.S02_AXI_WSTRB(S02_AXI_WSTRB), // input wire $63 : 0$ S02_AXI_WSTRB

.S02_AXI_WLAST(S02_AXI_WLAST), // input wire S02_AXI_WLAST

.S02_AXI_WVALID(S02_AXI_WVALID), // input wire S02_AXI_WVALID

.S02_AXI_WREADY(S02_AXI_WREADY), // output wire S02_AXI_WREADY

.S02_AXI_BID(S02_AXI_BID), // output wire $3 : 0$ S02_AXI_BID

.S02_AXI_BRESP(S02_AXI_BRESP), // output wire $1 : 0$ S02_AXI_BRESP

.S02_AXI_BVALID(S02_AXI_BVALID), // output wire S02_AXI_BVALID

.S02_AXI_BREADY(S02_AXI_BREADY), // input wire S02_AXI_BREADY

.S02_AXI_ARID(S02_AXI_ARID), // input wire $3 : 0$ S02_AXI_ARID

.S02_AXI_ARADDR(S02_AXI_ARADDR), // input wire $31 : 0$ S02_AXI_ARADDR

.S02_AXI_ARLEN(S02_AXI_ARLEN), // input wire $7 : 0$ S02_AXI_ARLEN

.S02_AXI_ARSIZE(S02_AXI_ARSIZE), // input wire $2 : 0$ S02_AXI_ARSIZE

.S02_AXI_ARBURST(S02_AXI_ARBURST), // input wire $1 : 0$ S02_AXI_ARBURST

.S02_AXI_ARLOCK(S02_AXI_ARLOCK), // input wire S02_AXI_ARLOCK

.S02_AXI_ARCACHE(S02_AXI_ARCACHE), // input wire $3 : 0$ S02_AXI_ARCACHE

.S02_AXI_ARPROT(S02_AXI_ARPROT), // input wire $2 : 0$ S02_AXI_ARPROT

.S02_AXI_ARQOS(S02_AXI_ARQOS), // input wire $3 : 0$ S02_AXI_ARQOS

.S02_AXI_ARVALID(S02_AXI_ARVALID), // input wire S02_AXI_ARVALID

.S02_AXI_ARREADY(S02_AXI_ARREADY), // output wire S02_AXI_ARREADY

.S02_AXI_RID(S02_AXI_RID), // output wire $3 : 0$ S02_AXI_RID

.S02_AXI_RDATA(S02_AXI_RDATA), // output wire $511 : 0$ S02_AXI_RDATA

.S02_AXI_RRESP(S02_AXI_RRESP), // output wire $1 : 0$ S02_AXI_RRESP

.S02_AXI_RLAST(S02_AXI_RLAST), // output wire S02_AXI_RLAST

.S02_AXI_RVALID(S02_AXI_RVALID), // output wire S02_AXI_RVALID

.S02_AXI_RREADY(S02_AXI_RREADY), // input wire S02_AXI_RREADY

//chnl 3

.S03_AXI_ARESET_OUT_N(S03_AXI_ARESET_OUT_N), // output wire S03_AXI_ARESET_OUT_N

.S03_AXI_ACLK(clk_75m), // input wire S03_AXI_ACLK

.S03_AXI_AWID(S03_AXI_AWID), // input wire $3 : 0$ S03_AXI_AWID

.S03_AXI_AWADDR(S03_AXI_AWADDR), // input wire $31 : 0$ S03_AXI_AWADDR

.S03_AXI_AWLEN(S03_AXI_AWLEN), // input wire $7 : 0$ S03_AXI_AWLEN

.S03_AXI_AWSIZE(S03_AXI_AWSIZE), // input wire $2 : 0$ S03_AXI_AWSIZE

.S03_AXI_AWBURST(S03_AXI_AWBURST), // input wire $1 : 0$ S03_AXI_AWBURS

.S03_AXI_AWLOCK(S03_AXI_AWLOCK), // input wire S03_AXI_AWLOCK

.S03_AXI_AWCACHE(S03_AXI_AWCACHE), // input wire $3 : 0$ S03_AXI_AWCACHE

.S03_AXI_AWPROT(S03_AXI_AWPROT), // input wire $2 : 0$ S03_AXI_AWPROT

.S03_AXI_AWQOS(S03_AXI_AWQOS), // input wire $3 : 0$ S03_AXI_AWQOS

.S03_AXI_AWVALID(S03_AXI_AWVALID), // input wire S03_AXI_AWVALID

.S03_AXI_AWREADY(S03_AXI_AWREADY), // output wire S03_AXI_AWREADY

.S03_AXI_WDATA(S03_AXI_WDATA), // input wire $511 : 0$ S03_AXI_WDATA

.S03_AXI_WSTRB(S03_AXI_WSTRB), // input wire $63 : 0$ S03_AXI_WSTRB

.S03_AXI_WLAST(S03_AXI_WLAST), // input wire S03_AXI_WLAST

.S03_AXI_WVALID(S03_AXI_WVALID), // input wire S03_AXI_WVALID

.S03_AXI_WREADY(S03_AXI_WREADY), // output wire S03_AXI_WREADY

.S03_AXI_BID(S03_AXI_BID), // output wire $3 : 0$ S03_AXI_BID

.S03_AXI_BRESP(S03_AXI_BRESP), // output wire $1 : 0$ S03_AXI_BRESP

.S03_AXI_BVALID(S03_AXI_BVALID), // output wire S03_AXI_BVALID

.S03_AXI_BREADY(S03_AXI_BREADY), // input wire S03_AXI_BREADY

.S03_AXI_ARID(S03_AXI_ARID), // input wire $3 : 0$ S03_AXI_ARID

.S03_AXI_ARADDR(S03_AXI_ARADDR), // input wire $31 : 0$ S03_AXI_ARADDR

.S03_AXI_ARLEN(S03_AXI_ARLEN), // input wire $7 : 0$ S03_AXI_ARLEN

.S03_AXI_ARSIZE(S03_AXI_ARSIZE), // input wire $2 : 0$ S03_AXI_ARSIZE

.S03_AXI_ARBURST(S03_AXI_ARBURST), // input wire $1 : 0$ S03_AXI_ARBURST

.S03_AXI_ARLOCK(S03_AXI_ARLOCK), // input wire S03_AXI_ARLOCK

.S03_AXI_ARCACHE(S03_AXI_ARCACHE), // input wire $3 : 0$ S03_AXI_ARCACHE

.S03_AXI_ARPROT(S03_AXI_ARPROT), // input wire $2 : 0$ S03_AXI_ARPROT

.S03_AXI_ARQOS(S03_AXI_ARQOS), // input wire $3 : 0$ S03_AXI_ARQOS

.S03_AXI_ARVALID(S03_AXI_ARVALID), // input wire S03_AXI_ARVALID

.S03_AXI_ARREADY(S03_AXI_ARREADY), // output wire S03_AXI_ARREADY

.S03_AXI_RID(S03_AXI_RID), // output wire $3 : 0$ S03_AXI_RID

.S03_AXI_RDATA(S03_AXI_RDATA), // output wire $511 : 0$ S03_AXI_RDATA

.S03_AXI_RRESP(S03_AXI_RRESP), // output wire $1 : 0$ S03_AXI_RRESP

.S03_AXI_RLAST(S03_AXI_RLAST), // output wire S03_AXI_RLAST

.S03_AXI_RVALID(S03_AXI_RVALID), // output wire S03_AXI_RVALID

.S03_AXI_RREADY(S03_AXI_RREADY), // input wire S03_AXI_RREADY

//master

//ddr4 awaddr

.M00_AXI_ARESET_OUT_N(c0_ddr4_aresetn_n), // output wire M00_AXI_ARESET_OUT_N

.M00_AXI_ACLK(c0_ddr4_clk), // input wire M00_AXI_ACLK

.M00_AXI_AWID(c0_ddr4_s_axi_awid), // output wire $7 : 0$ M00_AXI_AWID

.M00_AXI_AWADDR(c0_ddr4_s_axi_awaddr), // output wire $31 : 0$ M00_AXI_AWADDR

.M00_AXI_AWLEN(c0_ddr4_s_axi_awlen), // output wire $7 : 0$ M00_AXI_AWLEN

.M00_AXI_AWSIZE(c0_ddr4_s_axi_awsize), // output wire $2 : 0$ M00_AXI_AWSIZE

.M00_AXI_AWBURST(c0_ddr4_s_axi_awburst), // output wire $1 : 0$ M00_AXI_AWBURST

.M00_AXI_AWLOCK(c0_ddr4_s_axi_awlock), // output wire M00_AXI_AWLOCK

.M00_AXI_AWCACHE(c0_ddr4_s_axi_awcache), // output wire $3 : 0$ M00_AXI_AWCACHE

.M00_AXI_AWPROT(c0_ddr4_s_axi_awprot), // output wire $2 : 0$ M00_AXI_AWPROT

.M00_AXI_AWQOS(c0_ddr4_s_axi_awqos), // output wire $3 : 0$ M00_AXI_AWQOS

.M00_AXI_AWVALID(c0_ddr4_s_axi_awvalid), // output wire M00_AXI_AWVALID

.M00_AXI_AWREADY(c0_ddr4_s_axi_awready), // input wire M00_AXI_AWREADY

//ddr4 wdata

.M00_AXI_WDATA(c0_ddr4_s_axi_wdata), // output wire $511 : 0$ M00_AXI_WDATA

.M00_AXI_WSTRB(c0_ddr4_s_axi_wstrb), // output wire $63 : 0$ M00_AXI_WSTRB

.M00_AXI_WLAST(c0_ddr4_s_axi_wlast), // output wire M00_AXI_WLAST

.M00_AXI_WVALID(c0_ddr4_s_axi_wvalid), // output wire M00_AXI_WVALID

.M00_AXI_WREADY(c0_ddr4_s_axi_wready), // input wire M00_AXI_WREADY

//ddr4 w bresp

.M00_AXI_BID(c0_ddr4_s_axi_bid), // input wire $7 : 0$ M00_AXI_BID

.M00_AXI_BRESP(c0_ddr4_s_axi_bresp), // input wire $1 : 0$ M00_AXI_BRESP

.M00_AXI_BVALID(c0_ddr4_s_axi_bvalid), // input wire M00_AXI_BVALID

.M00_AXI_BREADY(c0_ddr4_s_axi_bready), // output wire M00_AXI_BREADY

//ddr4 araddr

.M00_AXI_ARID(c0_ddr4_s_axi_arid), // output wire $7 : 0$ M00_AXI_ARID

.M00_AXI_ARADDR(c0_ddr4_s_axi_araddr), // output wire $31 : 0$ M00_AXI_ARADDR

.M00_AXI_ARLEN(c0_ddr4_s_axi_arlen), // output wire $7 : 0$ M00_AXI_ARLEN

.M00_AXI_ARSIZE(c0_ddr4_s_axi_arsize), // output wire $2 : 0$ M00_AXI_ARSIZE

.M00_AXI_ARBURST(c0_ddr4_s_axi_arburst), // output wire $1 : 0$ M00_AXI_ARBURST

.M00_AXI_ARLOCK(c0_ddr4_s_axi_arlock), // output wire M00_AXI_ARLOCK

.M00_AXI_ARCACHE(c0_ddr4_s_axi_arcache), // output wire $3 : 0$ M00_AXI_ARCACHE

.M00_AXI_ARPROT(c0_ddr4_s_axi_arprot), // output wire $2 : 0$ M00_AXI_ARPROT

.M00_AXI_ARQOS(c0_ddr4_s_axi_arqos), // output wire $3 : 0$ M00_AXI_ARQOS

.M00_AXI_ARVALID(c0_ddr4_s_axi_arvalid), // output wire M00_AXI_ARVALID

.M00_AXI_ARREADY(c0_ddr4_s_axi_arready), // input wire M00_AXI_ARREADY

//ddr4 rdata

.M00_AXI_RID(c0_ddr4_s_axi_rid), // input wire $7 : 0$ M00_AXI_RID

.M00_AXI_RDATA(c0_ddr4_s_axi_rdata), // input wire $511 : 0$ M00_AXI_RDATA

.M00_AXI_RRESP(c0_ddr4_s_axi_rresp), // input wire $1 : 0$ M00_AXI_RRESP

.M00_AXI_RLAST(c0_ddr4_s_axi_rlast), // input wire M00_AXI_RLAST

.M00_AXI_RVALID(c0_ddr4_s_axi_rvalid), // input wire M00_AXI_RVALID

.M00_AXI_RREADY(c0_ddr4_s_axi_rready) // output wire M00_AXI_RREADY

);

可以看到interconnect的从接口配置了4组，分别对应4个通道，主接口配置了1组，连接到ddr4。

因为interconnect中4个axi4的从接口是相同功能，只需要将接口信号加上后缀，分别对应四个通道，与ddr4读写控制模块连接。ddr4读写控制模块来发起读写指令，那么4组ddr4读写模块就可以控制4组axi4的通道来发起读写请求。

四、Ddr4读写模块例化

ddr4_axi_wr_ctrl inst_ddr4_axi_wr_ctrl_0 (

.sclk (clk_75m),

.rst (~S00_AXI_ARESET_OUT_N),

//user_sport

.wr_start (wr_start_0),

.awaddr_in (awaddr_in_0),

.awlen_in (awlen_in_0),

.wdata_in (wdata_in_0),

.awaddr_cnt (awaddr_cnt_0),

.wr_busy (wr_busy_0),

//wr_address_ports

.awid (S00_AXI_AWID),

.awaddr (S00_AXI_AWADDR),

.awlen (S00_AXI_AWLEN),

.awsize (S00_AXI_AWSIZE),

.awburst (S00_AXI_AWBURST),

.S_AXI_AWLOCK (S00_AXI_AWLOCK),

.S_AXI_AWCACHE (S00_AXI_AWCACHE),

.S_AXI_AWPROT (S00_AXI_AWPROT),

.S_AXI_AWQOS (S00_AXI_AWQOS),

.awready (S00_AXI_AWREADY),

.awvalid (S00_AXI_AWVALID),

//wr_data_ports

.wready (S00_AXI_WREADY),

.wvalid (S00_AXI_WVALID),

.wdata (S00_AXI_WDATA),

.wstrb (S00_AXI_WSTRB),

.wlast (S00_AXI_WLAST),

//wr_responce_ports

.bid (S00_AXI_BID),

.bresp (S00_AXI_BRESP),

.bvalid (S00_AXI_BVALID),

.bready (S00_AXI_BREADY)

);

复制代码

ddr4_axi_rd_ctrl inst_ddr4_axi_rd_ctrl_0
(
  .sclk       			(clk_75m),
  .rst        			(~S00_AXI_ARESET_OUT_N),
//user_sports
  .rd_start   			(rd_start_0),
  .araddr_in  			(araddr_in_0),
  .arlen_in   			(arlen_in_0),
  .rd_data    		(rd_data_0),
  .rd_en      		(rd_en_0),
  .araddr_cnt 			(araddr_cnt_0),
  .rd_end  			(rd_end_0),
  .rd_busy  			(rd_busy_0),
//rd_address_ports
  .arready   			(S00_AXI_ARREADY),
  .arvalid   			(S00_AXI_ARVALID),
  .arid      			(S00_AXI_ARID),
  .araddr    			(S00_AXI_ARADDR),
  .arlen     			(S00_AXI_ARLEN),
  .arsize    			(S00_AXI_ARSIZE),
  .arburst   			(S00_AXI_ARBURST),
  .S_AXI_ARLOCK 		(S00_AXI_ARLOCK),
  .S_AXI_ARCACHE 		(S00_AXI_ARCACHE),
  .S_AXI_ARPROT 		(S00_AXI_ARPROT),
  .S_AXI_ARQOS  		(S00_AXI_ARQOS),
	//rd_data_ports
  .rid       			(S00_AXI_RID),
  .rdata     			(S00_AXI_RDATA),
  .rresp     			(S00_AXI_RRESP),
  .rlast     			(S00_AXI_RLAST),
  .rvalid    			(S00_AXI_RVALID),
  .rready    			(S00_AXI_RREADY)
);

因为篇幅原因，这里提供通道0的读写控制模块的例化。另外3个通道的读写控制模块只需要将接口信号与interconnect和测试模块对应即可。

五、通道0测试模块例化

chnl_test_0 inst_chnl_test_0

(

.chnl_clk_0 (clk_75m),

.chnl_rst_0 (~S00_AXI_ARESET_OUT_N),

.wr_start_0 (wr_start_0),

.awaddr_in_0 (awaddr_in_0),

.awlen_in_0 (awlen_in_0),

.wdata_in_0 (wdata_in_0),

.wvalid_0 (S00_AXI_WVALID),

.wready_0 (S00_AXI_WREADY),

.awaddr_cnt_0 (awaddr_cnt_0),

.wr_busy_0 (wr_busy_0),

.rd_start_0 (rd_start_0),

.araddr_in_0 (araddr_in_0),

.arlen_in_0 (arlen_in_0),

.rd_data_0 (rd_data_0),

.rd_en_0 (rd_en_0),

.araddr_cnt_0 (araddr_cnt_0),

.rd_end_0 (rd_end_0),

.rd_busy_0 (rd_busy_0)

);

例化说明：chnl_test_0为通道0的测试模块，本模块的复位信号由interconnect提供。

六、ddr4 IP例化

ddr4_0 u_ddr4_0

(

.sys_rst (rst),

.c0_sys_clk_p (clk_300_p), // input wire c0_sys_clk_p

.c0_sys_clk_n (clk_300_n), // input wire c0_sys_clk_n

.c0_init_calib_complete (c0_init_calib_complete),

.c0_ddr4_act_n (c0_ddr4_act_n),

.c0_ddr4_adr (c0_ddr4_adr),

.c0_ddr4_ba (c0_ddr4_ba),

.c0_ddr4_bg (c0_ddr4_bg),

.c0_ddr4_cke (c0_ddr4_cke),

.c0_ddr4_odt (c0_ddr4_odt),

.c0_ddr4_cs_n (c0_ddr4_cs_n),

.c0_ddr4_ck_t (c0_ddr4_ck_t),

.c0_ddr4_ck_c (c0_ddr4_ck_c),

.c0_ddr4_reset_n (c0_ddr4_reset_n_int),

.c0_ddr4_dm_dbi_n (c0_ddr4_dm_dbi_n),

.c0_ddr4_dq (c0_ddr4_dq),

.c0_ddr4_dqs_c (c0_ddr4_dqs_c),

.c0_ddr4_dqs_t (c0_ddr4_dqs_t),

.c0_ddr4_ui_clk (c0_ddr4_clk),

.c0_ddr4_ui_clk_sync_rst (c0_ddr4_rst),

// Slave Interface Write Address Ports

.c0_ddr4_aresetn (c0_ddr4_aresetn), // input wire c0_ddr4_aresetn

.c0_ddr4_s_axi_awid (c0_ddr4_s_axi_awid), //input wire $7 : 0$ c0_ddr4_s_axi_awid

.c0_ddr4_s_axi_awaddr (c0_ddr4_s_axi_awaddr),//input wire $31 : 0$ c0_ddr4_s_axi_awaddr

.c0_ddr4_s_axi_awlen (c0_ddr4_s_axi_awlen), // input wire $7 : 0$ c0_ddr4_s_axi_awlen

.c0_ddr4_s_axi_awsize (c0_ddr4_s_axi_awsize), // input wire $2 : 0$ c0_ddr4_s_axi_awsize

.c0_ddr4_s_axi_awburst (c0_ddr4_s_axi_awburst), // input wire $1 : 0$ c0_ddr4_s_axi_awburst

.c0_ddr4_s_axi_awlock (c0_ddr4_s_axi_awlock),

.c0_ddr4_s_axi_awcache (c0_ddr4_s_axi_awcache),//(c0_ddr4_s_axi_awcache),//input wire $3 : 0$ c0_ddr4_s_axi_awcache

.c0_ddr4_s_axi_awprot (c0_ddr4_s_axi_awprot),//(c0_ddr4_s_axi_awprot),// input wire $2 : 0$ c0_ddr4_s_axi_awprot

.c0_ddr4_s_axi_awqos (c0_ddr4_s_axi_awqos),

.c0_ddr4_s_axi_awvalid (c0_ddr4_s_axi_awvalid), // input wire c0_ddr4_s_axi_awvalid

.c0_ddr4_s_axi_awready (c0_ddr4_s_axi_awready), // output wire c0_ddr4_s_axi_awready

// Slave Interface Write Data Ports

.c0_ddr4_s_axi_wdata (c0_ddr4_s_axi_wdata), // input wire $511 : 0$ c0_ddr4_s_axi_wdata

.c0_ddr4_s_axi_wstrb (c0_ddr4_s_axi_wstrb), // input wire $63 : 0$ c0_ddr4_s_axi_wstrb

.c0_ddr4_s_axi_wlast (c0_ddr4_s_axi_wlast), // input wire c0_ddr4_s_axi_wlast

.c0_ddr4_s_axi_wvalid (c0_ddr4_s_axi_wvalid), // input wire c0_ddr4_s_axi_wvalid

.c0_ddr4_s_axi_wready (c0_ddr4_s_axi_wready), // output wire c0_ddr4_s_axi_wready

// Slave Interface Write Response Ports

.c0_ddr4_s_axi_bid (c0_ddr4_s_axi_bid), // output wire $7 : 0$ c0_ddr4_s_axi_bid

.c0_ddr4_s_axi_bresp (c0_ddr4_s_axi_bresp), // output wire $1 : 0$ c0_ddr4_s_axi_bresp

.c0_ddr4_s_axi_bvalid (c0_ddr4_s_axi_bvalid), // output wire c0_ddr4_s_axi_bvalid

.c0_ddr4_s_axi_bready (c0_ddr4_s_axi_bready), // input wire c0_ddr4_s_axi_bready

// Slave Interface Read Address Ports

.c0_ddr4_s_axi_arid (c0_ddr4_s_axi_arid), // input wire $7 : 0$ c0_ddr4_s_axi_arid

.c0_ddr4_s_axi_araddr (c0_ddr4_s_axi_araddr), // input wire $31 : 0$ c0_ddr4_s_axi_araddr

.c0_ddr4_s_axi_arlen (c0_ddr4_s_axi_arlen), // input wire $7 : 0$ c0_ddr4_s_axi_arlen

.c0_ddr4_s_axi_arsize (c0_ddr4_s_axi_arsize), // input wire $2 : 0$ c0_ddr4_s_axi_arsize

.c0_ddr4_s_axi_arburst (c0_ddr4_s_axi_arburst), // input wire $1 : 0$ c0_ddr4_s_axi_arburst

.c0_ddr4_s_axi_arlock (c0_ddr4_s_axi_arlock),

.c0_ddr4_s_axi_arcache (c0_ddr4_s_axi_arcache),// input wire $3 : 0$ c0_ddr4_s_axi_arcache

.c0_ddr4_s_axi_arprot (c0_ddr4_s_axi_arprot),

.c0_ddr4_s_axi_arqos (c0_ddr4_s_axi_arqos),

.c0_ddr4_s_axi_arvalid (c0_ddr4_s_axi_arvalid),// input wire c0_ddr4_s_axi_arvalid

.c0_ddr4_s_axi_arready (c0_ddr4_s_axi_arready), // output wire c0_ddr4_s_axi_arready

// Slave Interface Read Data Ports

.c0_ddr4_s_axi_rid (c0_ddr4_s_axi_rid), // output wire $7 : 0$ c0_ddr4_s_axi_rid

.c0_ddr4_s_axi_rdata (c0_ddr4_s_axi_rdata), // output wire $511 : 0$ c0_ddr4_s_axi_rdata

.c0_ddr4_s_axi_rresp (c0_ddr4_s_axi_rresp), // output wire $1 : 0$ c0_ddr4_s_axi_rresp

.c0_ddr4_s_axi_rlast (c0_ddr4_s_axi_rlast), // output wire c0_ddr4_s_axi_rlast

.c0_ddr4_s_axi_rvalid (c0_ddr4_s_axi_rvalid), // output wire c0_ddr4_s_axi_rvalid

.c0_ddr4_s_axi_rready (c0_ddr4_s_axi_rready), // input wire c0_ddr4_s_axi_rready

// Debug Port

.dbg_clk (dbg_clk),

.dbg_bus (dbg_bus)

);

例化说明：Ddr4 IP的时钟在配置时选择的差分时钟，接口信号连接到interconnect的主接口。

七、章节总结

在本章节将之前讲过的功能模块与IP互连，从而实现使用四个测试通道来控制一个ddr4内存的读写，使用interconnect实现ddr4的多通道读写功能。

本文章由威三学社出品

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