Getting Started with ARM and IMX6ULL
1. Core Understanding of ARM Ecosystem
1. ARM Company Positioning and Business Model
ARM was founded in November 1990, formerly known as Acorn Computer Company. Its core business focuses on RISC (Reduced Instruction Set) processor core design. ARM does not manufacture chips directly but collaborates with semiconductor manufacturers (such as NXP, ST, Samsung, etc.) through a core licensing model.
- Core Value: Provides comprehensive technical support for ARM architecture, including processor cores, development tools, bus architecture, peripheral solutions, etc.
- Ecosystem Advantage: Partners cover the globe, spawning a vast number of ARM-based chips, dominating fields like embedded systems and mobile devices.
2. ARM Processor Series Classification (by Application Scenario)
ARM processors are divided into three major series based on functional positioning, catering to different embedded scenarios:
| Series Type | Core Representatives | Application Scenarios | Core Features |
|---|---|---|---|
| Application-Level (Cortex-A) | Cortex-A9, A8, A7, A5 | Smartphones, tablets, set-top boxes, IMX6ULL, etc. | High performance, multi-core support, capable of running Linux/Android |
| Real-Time-Level (Cortex-R) | Cortex-R4, R4F | Automotive electronics, disk controllers, industrial real-time control | Low latency, high reliability, real-time response |
| Microcontroller-Level (Cortex-M) | Cortex-M0, M3, M4 | Microcontrollers, sensors, smart home devices, motor controllers | Low power consumption, low cost, high integration |
2. Core Analysis of IMX6ULL Chip
IMX6ULL is a single-core Cortex-A7 architecture processor launched by NXP, belonging to the low-power, low-cost variant of the i.MX6 series. It is a popular choice for embedded bare-metal development and Linux application development.
1. Core Hardware Specifications
- Processor Core: Single-core ARM Cortex-A7, maximum frequency of 900MHz, integrated 128KB L2 cache;
- Memory Interfaces: Supports LPDDR2, DDR3, DDR3L, NAND/NOR flash, eMMC, Quad SPI, etc.;
- Peripheral Interfaces: USB, Ethernet, parallel LCD (supports 1366x768 resolution), camera sensors, audio, SD/MMC, etc.;
- Power Management: Built-in PMU (Power Management Unit), simplifying external power supply design and reducing power consumption.
2. Typical Application Scenarios
- Consumer Electronics: Smart home terminals, IoT gateways, POS machines;
- Industrial Control: HMI human-machine interfaces, sensor data acquisition nodes;
- Automotive Electronics: Car dashboards, assisted driving modules;
- Advantages: Balances performance and power consumption, industrial-grade versions support wide temperature ranges, adapting to harsh environments.
3. Typical Applications of Cortex-M Series (Essential Knowledge for Beginners)
The Cortex-M series is a common choice for embedded beginners, characterized by low power consumption and ease of use. Mainstream solutions include:
1. NXP Cortex-M0 Solutions
- Representative Chips: LPC1100L, LPC11D00, LPC12D00;
- Application Scenarios: LED controllers, temperature controllers, blood glucose meters, household appliances;
- Core Advantage: Extremely low power consumption, suitable for simple control logic, low cost.
2. ST Cortex-M3 Solutions (STM32 Series)
- Representative Chips: STM3210x, STM32F103, etc. (36-144 pins, 16KB-512KB flash);
- Core Advantage: Rich peripherals including USB, Ethernet, CAN, supporting complex functions like motor control and audio processing;
- Typical Applications: Motor drives, medical devices, consumer electronics (printers, alarm systems).
4. Fundamentals of ARM Assembly Programming (Core for Practical Work)
Assembly is the foundation of ARM bare-metal development. Mastering program structure and core instructions is essential to understanding the processor's underlying workings.
1. Basic Framework of ARM Assembly Programs
ARM assembly uses pseudo-instructions to guide the assembler. The core structure is fixed and must strictly follow format specifications (instructions must be indented with tabs):
armasm
AREA reset, CODE, READONLY ; Define a read-only code segment named reset (reset vector segment)
CODE32 ; Specify 32-bit ARM instruction set (use THUMB for Thumb)
ENTRY ; Mark the program entry (only one ENTRY per project)
; Functional code area
start ; Label (jump target, no indentation)
MOV R0, #0x01 ; R0 = 1 (immediate value assignment)
MOV R1, R0 ; R1 = R0 (register-to-register data copy)
B . ; Infinite loop (stay on current instruction)
END ; Mark the end of the file; the assembler stops processing2. Key Pseudo-Instruction Analysis
Pseudo-instructions are "compilation directives" for the assembler, not executed by the processor but determining program structure:
| Pseudo-Instruction | Function Description |
|---|---|
| AREA | Define code/data/stack segments. Format: AREA segment_name, segment_attribute, access_permission (e.g., DATA/CODE, READWRITE/READONLY) |
| CODE32/THUMB | Specify instruction set type: 32-bit ARM (full functionality) or 16-bit Thumb (high code density) |
| ENTRY | Mark the program entry; the linker relies on this to locate the first instruction after reset |
| END | Mark the end of the file; subsequent content is ignored |
3. Core Assembly Instructions: Data Transfer (MOV/MVN)
Data transfer is the foundation of assembly programming, responsible for moving data between registers or from immediate values to registers:
(1) MOV Instruction (Data Move/Assignment)
Function: Transfer immediate values, register values, or shifted register values to the target register (similar to = in C)
| Instruction Format | Example Code | Function Explanation |
|---|---|---|
| MOV{S} Rd, #const | MOV R0, #0x0A | R0 = 10 (hex 0x0A, complies with 12-bit immediate rule) |
| MOV{S} Rd, Rm | MOV R1, R0 | R1 = R0 (register-to-register copy) |
| MOV{S} Rd, Rm, | MOV R2, R0, LSL #2 | R0 shifted left by 2 bits (×4) and stored in R2 |
Key Note : ARM immediate values must comply with the "12-bit rule" (8-bit constant + 4-bit cyclic shift ×2). For example, #0x80000000 is legal, while #0x12345678 is illegal (exceeds combination range).
(2) MVN Instruction (Bitwise NOT Transfer)
Function: Transfer the bitwise NOT of the source operand to the target register (similar to ~ in C)
| Instruction Format | Example Code | Function Explanation |
|---|---|---|
| MVN{S} Rd, #const | MVN R0, #0x00 | R0 = 0xFFFFFFFF (NOT of 0x00) |
| MVN{S} Rd, Rm | MVN R1, R0 | R1 = ~R0 (bitwise NOT of register value) |
Practical Example: Simple Arithmetic in Assembly
Requirement: R0=3 → R1=3×4 → R2=~R1 → R3=~R1+1 (final R3=-12, two's complement)
armasm
AREA calc_demo, CODE, READONLY
CODE32
ENTRY
start
MOV R0, #0x03 ; R0 = 3
MOV R1, R0, LSL #2 ; R1 = 3×4 = 12 (shift left by 2 bits)
MVN R2, R1 ; R2 = ~12 = 0xFFFFFFF3
ADD R3, R2, #0x01 ; R3 = ~12 + 1 = -12 (two's complement)
B . ; Infinite loop to halt
END4. Assembly Programming Pitfalls
- Indentation Rules: Pseudo-instructions and processor instructions must be indented with tabs; labels (e.g., start) must not be indented, or the assembler will report errors;
- Instruction Set Matching: Thumb instructions cannot be mixed in CODE32 segments to avoid execution exceptions;
- Immediate Value Legality: Immediate values exceeding the 12-bit rule must be split (e.g.,
#0x1234must be split intoMOV R0,#0x34+MOV R0,R0,LSL#8+ORR R0,#0x12); - ENTRY Uniqueness: Only one ENTRY per project; otherwise, the linker cannot locate the program entry.
5. Key Points for ARM Bare-Metal Development Environment Setup
For ARM bare-metal development based on IMX6ULL, the core lies in setting up the toolchain and compilation process:
1. Core Toolchain
- Compiler: ARM-GCC (cross-compiler, adapted for ARM architecture) or Keil uVision4/5;
- Debugging Tools: JTAG debugger (e.g., J-Link), serial debugging assistant;
- Auxiliary Tools: Linker script (defines code/data segment address allocation), startup file (initializes stack, interrupt vector table).
2. Key Development Principles
- Register Protection: Function calls must save registers like R0-R3 and LR via the stack to avoid data loss or return exceptions;
- Address Alignment: ARM instructions require 32-bit alignment (Thumb requires 16-bit), otherwise data exceptions are triggered;
- Practical Priority: Master assembly basics first (as in the examples here), then transition to bare-metal programming of IMX6ULL peripherals like GPIO and UART.