***********************************************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: modelsim *
* Compiled on: Tue Jan 27 13:36:48 2026 *
* *
***********************************************************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*---------------------------------------------------------------------------------------------------------------------*
* secureip | verilog | secureip | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* unisim | vhdl | unisim | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* unimacro | vhdl | unimacro | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* unifast | vhdl | unifast | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* unisim | verilog | unisims_ver | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* unimacro | verilog | unimacro_ver | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* unifast | verilog | unifast_ver | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* simprim | verilog | simprims_ver | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xpm | vhdl | xpm | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xpm | verilog | xpm | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xilinx_vip | verilog | xilinx_vip | 0 | 47 *
*---------------------------------------------------------------------------------------------------------------------*
* ahblite_axi_bridge_v3_0_13 | vhdl | ahblite_axi_bridge_v3_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* audio_clock_recovery_v1_0 | verilog | audio_clock_recovery_v1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* audio_tpg_v1_0_0 | verilog | audio_tpg_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* av_pat_gen_v1_0_0 | verilog | av_pat_gen_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_infrastructure_v1_1_0 | verilog | axis_infrastructure_v1_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_protocol_checker_v2_0_2 | verilog | axis_protocol_checker_v2_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_ahblite_bridge_v3_0_15 | vhdl | axi_ahblite_bridge_v3_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_amm_bridge_v1_0_8 | verilog | axi_amm_bridge_v1_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_chip2chip_v5_0_4 | verilog | axi_chip2chip_v5_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_infrastructure_v1_1_0 | verilog | axi_infrastructure_v1_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_jtag_v1_0_0 | verilog | axi_jtag_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_lite_ipif_v3_0_4 | vhdl | axi_lite_ipif_v3_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_pcie3_v3_0_8 | verilog | axi_pcie3_v3_0_8 | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_perf_mon_v5_0_20 | verilog | axi_perf_mon_v5_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* blk_mem_gen_v8_3_6 | verilog | blk_mem_gen_v8_3_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* blk_mem_gen_v8_4_2 | verilog | blk_mem_gen_v8_4_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* bsip_v1_1_0 | vhdl | bsip_v1_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* bsip_v1_1_0 | verilog | bsip_v1_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* bs_mux_v1_0_0 | verilog | bs_mux_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* clk_vip_v1_0_2 | verilog | clk_vip_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cmac_usplus_v2_4_4 | verilog | cmac_usplus_v2_4_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cmac_usplus_v2_5_0 | verilog | cmac_usplus_v2_5_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cmac_v2_3_4 | verilog | cmac_v2_3_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cmac_v2_4_0 | verilog | cmac_v2_4_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* compact_gt_v1_0_4 | vhdl | compact_gt_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* dist_mem_gen_v8_0_12 | verilog | dist_mem_gen_v8_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ecc_v2_0_12 | verilog | ecc_v2_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* emc_common_v3_0_5 | vhdl | emc_common_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_0_2 | vhdl | ethernet_1_10_25g_v2_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_0_2 | verilog | ethernet_1_10_25g_v2_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_1_1 | vhdl | ethernet_1_10_25g_v2_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_1_1 | verilog | ethernet_1_10_25g_v2_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_2_0 | vhdl | ethernet_1_10_25g_v2_2_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ethernet_1_10_25g_v2_2_0 | verilog | ethernet_1_10_25g_v2_2_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fifo_generator_v13_0_6 | vhdl | fifo_generator_v13_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fifo_generator_v13_1_4 | vhdl | fifo_generator_v13_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fifo_generator_v13_1_4 | verilog | fifo_generator_v13_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fifo_generator_v13_2_3 | vhdl | fifo_generator_v13_2_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fifo_generator_v13_2_3 | verilog | fifo_generator_v13_2_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fit_timer_v2_0_9 | vhdl | fit_timer_v2_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* generic_baseblocks_v2_1_0 | verilog | generic_baseblocks_v2_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gigantic_mux | verilog | gigantic_mux | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gig_ethernet_pcs_pma_v16_1_5 | vhdl | gig_ethernet_pcs_pma_v16_1_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gig_ethernet_pcs_pma_v16_1_5 | verilog | gig_ethernet_pcs_pma_v16_1_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gmii_to_rgmii_v4_0_7 | vhdl | gmii_to_rgmii_v4_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gtwizard_ultrascale_v1_5_4 | verilog | gtwizard_ultrascale_v1_5_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gtwizard_ultrascale_v1_6_10 | verilog | gtwizard_ultrascale_v1_6_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* gtwizard_ultrascale_v1_7_5 | verilog | gtwizard_ultrascale_v1_7_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* hbm_v1_0_2 | verilog | hbm_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* hdcp22_cipher_v1_0_3 | verilog | hdcp22_cipher_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* hdcp22_rng_v1_0_1 | verilog | hdcp22_rng_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* hdcp_keymngmt_blk_v1_0_0 | verilog | hdcp_keymngmt_blk_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* hdcp_v1_0_3 | verilog | hdcp_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* high_speed_selectio_wiz_v3_2_3 | verilog | high_speed_selectio_wiz_v3_2_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* high_speed_selectio_wiz_v3_3_1 | verilog | high_speed_selectio_wiz_v3_3_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* high_speed_selectio_wiz_v3_4_1 | verilog | high_speed_selectio_wiz_v3_4_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* high_speed_selectio_wiz_v3_5_0 | verilog | high_speed_selectio_wiz_v3_5_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* i2s_receiver_v1_0_2 | verilog | i2s_receiver_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* i2s_transmitter_v1_0_2 | verilog | i2s_transmitter_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ibert_lib_v1_0_5 | verilog | ibert_lib_v1_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_clause74_fec_v1_0_2 | verilog | ieee802d3_clause74_fec_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* interlaken_v2_4_2 | verilog | interlaken_v2_4_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* in_system_ibert_v1_0_8 | verilog | in_system_ibert_v1_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* iomodule_v3_1_4 | vhdl | iomodule_v3_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* jesd204c_v4_0_0 | verilog | jesd204c_v4_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* jesd204_v7_2_4 | verilog | jesd204_v7_2_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* jtag_axi | verilog | jtag_axi | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lib_cdc_v1_0_2 | vhdl | lib_cdc_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lib_pkg_v1_0_2 | vhdl | lib_pkg_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lmb_bram_if_cntlr_v4_0_15 | vhdl | lmb_bram_if_cntlr_v4_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lmb_v10_v3_0_9 | vhdl | lmb_v10_v3_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ltlib_v1_0_0 | verilog | ltlib_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lut_buffer_v1_0_0 | verilog | lut_buffer_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lut_buffer_v2_0_0 | verilog | lut_buffer_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* l_ethernet_v2_3_4 | verilog | l_ethernet_v2_3_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* l_ethernet_v2_4_0 | verilog | l_ethernet_v2_4_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mammoth_transcode_v1_0_0 | verilog | mammoth_transcode_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* microblaze_v10_0_7 | vhdl | microblaze_v10_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* microblaze_v11_0_0 | vhdl | microblaze_v11_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* microblaze_v9_5_4 | vhdl | microblaze_v9_5_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mii_to_rmii_v2_0_20 | vhdl | mii_to_rmii_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mipi_csi2_rx_ctrl_v1_0_8 | verilog | mipi_csi2_rx_ctrl_v1_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mipi_csi2_tx_ctrl_v1_0_4 | verilog | mipi_csi2_tx_ctrl_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mipi_dphy_v4_1_2 | verilog | mipi_dphy_v4_1_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mipi_dsi_tx_ctrl_v1_0_7 | verilog | mipi_dsi_tx_ctrl_v1_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mutex_v2_1_10 | vhdl | mutex_v2_1_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* nvmehc_v1_0_0 | verilog | nvmehc_v1_0_0 | 0 | 63 *
*---------------------------------------------------------------------------------------------------------------------*
* oddr_v1_0_0 | verilog | oddr_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pci32_v5_0_12 | vhdl | pci32_v5_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pci32_v5_0_12 | verilog | pci32_v5_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pci64_v5_0_11 | vhdl | pci64_v5_0_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pci64_v5_0_11 | verilog | pci64_v5_0_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pcie_jtag_v1_0_0 | verilog | pcie_jtag_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pc_cfr_v6_0_7 | vhdl | pc_cfr_v6_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pc_cfr_v6_1_3 | vhdl | pc_cfr_v6_1_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pc_cfr_v6_2_1 | vhdl | pc_cfr_v6_2_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* picxo | vhdl | picxo | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* qdma_v3_0_0 | verilog | qdma_v3_0_0 | 0 | 1447 *
*---------------------------------------------------------------------------------------------------------------------*
* rama_v1_1_0_lib | vhdl | rama_v1_1_0_lib | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* roe_framer_v1_0_0 | verilog | roe_framer_v1_0_0 | 0 | 17 *
*---------------------------------------------------------------------------------------------------------------------*
* rst_vip_v1_0_2 | verilog | rst_vip_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* smartconnect_v1_0 | verilog | smartconnect_v1_0 | 0 | 17 *
*---------------------------------------------------------------------------------------------------------------------*
* sd_fec_v1_0_1 | verilog | sd_fec_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* sem_ultra_v3_1_9 | verilog | sem_ultra_v3_1_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* sem_v4_1_11 | verilog | sem_v4_1_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* sim_clk_gen_v1_0_2 | verilog | sim_clk_gen_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* sim_rst_gen_v1_0_2 | verilog | sim_rst_gen_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* stm_v1_0 | verilog | stm_v1_0 | 0 | 41 *
*---------------------------------------------------------------------------------------------------------------------*
* stm_v1_0_0 | verilog | stm_v1_0_0 | 0 | 181 *
*---------------------------------------------------------------------------------------------------------------------*
* system_cache_v4_0_5 | vhdl | system_cache_v4_0_5 | 0 | 4 *
*---------------------------------------------------------------------------------------------------------------------*
* ta_dma_v1_0_2 | verilog | ta_dma_v1_0_2 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* tcc_decoder_3gpplte_v3_0_6 | vhdl | tcc_decoder_3gpplte_v3_0_6 | 0 | 18 *
*---------------------------------------------------------------------------------------------------------------------*
* ten_gig_eth_mac_v15_1_6 | verilog | ten_gig_eth_mac_v15_1_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ten_gig_eth_pcs_pma_v6_0_14 | verilog | ten_gig_eth_pcs_pma_v6_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* timer_sync_1588_v1_2_4 | vhdl | timer_sync_1588_v1_2_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* timer_sync_1588_v1_2_4 | verilog | timer_sync_1588_v1_2_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tmr_inject_v1_0_3 | vhdl | tmr_inject_v1_0_3 | 0 | 5 *
*---------------------------------------------------------------------------------------------------------------------*
* tmr_manager_v1_0_4 | vhdl | tmr_manager_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tmr_voter_v1_0_2 | vhdl | tmr_voter_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tsn_endpoint_ethernet_mac_block_v1_0_3 | vhdl | tsn_endpoint_ethernet_mac_block_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tsn_endpoint_ethernet_mac_block_v1_0_3 | verilog | tsn_endpoint_ethernet_mac_block_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* uhdsdi_gt_v1_0_3 | vhdl | uhdsdi_gt_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* uhdsdi_gt_v1_0_3 | verilog | uhdsdi_gt_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* usxgmii_v1_0_4 | verilog | usxgmii_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* util_idelay_ctrl_v1_0_1 | verilog | util_idelay_ctrl_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* util_reduced_logic_v2_0_4 | verilog | util_reduced_logic_v2_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* util_vector_logic_v2_0_1 | verilog | util_vector_logic_v2_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ba317 | vhdl | ba317 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vfb_v1_0_12 | verilog | vfb_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* video_frame_crc_v1_0_1 | verilog | video_frame_crc_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_edid_v1_0_0 | vhdl | vid_edid_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_edid_v1_0_0 | verilog | vid_edid_v1_0_0 | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_phy_controller_v2_1_4 | vhdl | vid_phy_controller_v2_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_phy_controller_v2_1_4 | verilog | vid_phy_controller_v2_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_phy_controller_v2_2_2 | vhdl | vid_phy_controller_v2_2_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* vid_phy_controller_v2_2_2 | verilog | vid_phy_controller_v2_2_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_axi4s_remap_v1_0_10 | verilog | v_axi4s_remap_v1_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_csc_v1_0_12 | verilog | v_csc_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_deinterlacer_v4_0_12 | vhdl | v_deinterlacer_v4_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_deinterlacer_v5_0_12 | verilog | v_deinterlacer_v5_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_demosaic_v1_0_4 | verilog | v_demosaic_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_frmbuf_rd_v2_1_1 | verilog | v_frmbuf_rd_v2_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_frmbuf_wr_v2_1_1 | verilog | v_frmbuf_wr_v2_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_gamma_lut_v1_0_4 | verilog | v_gamma_lut_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hcresampler_v1_0_12 | verilog | v_hcresampler_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hdmi_rx_v2_0_0 | verilog | v_hdmi_rx_v2_0_0 | 0 | 51 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hdmi_rx_v3_0_0 | verilog | v_hdmi_rx_v3_0_0 | 0 | 428 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hdmi_tx_v2_0_0 | verilog | v_hdmi_tx_v2_0_0 | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hdmi_tx_v3_0_0 | verilog | v_hdmi_tx_v3_0_0 | 0 | 117 *
*---------------------------------------------------------------------------------------------------------------------*
* v_hscaler_v1_0_12 | verilog | v_hscaler_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_letterbox_v1_0_12 | verilog | v_letterbox_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_mix_v3_0_2 | verilog | v_mix_v3_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_multi_scaler_v1_0_0 | verilog | v_multi_scaler_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_scenechange_v1_0_0 | verilog | v_scenechange_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_sdi_rx_vid_bridge_v2_0_0 | verilog | v_sdi_rx_vid_bridge_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_sdi_v3_0_8 | verilog | v_smpte_sdi_v3_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_uhdsdi_rx_v1_0_0 | vhdl | v_smpte_uhdsdi_rx_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_uhdsdi_rx_v1_0_0 | verilog | v_smpte_uhdsdi_rx_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_uhdsdi_tx_v1_0_0 | vhdl | v_smpte_uhdsdi_tx_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_uhdsdi_tx_v1_0_0 | verilog | v_smpte_uhdsdi_tx_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_smpte_uhdsdi_v1_0_6 | verilog | v_smpte_uhdsdi_v1_0_6 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* v_tpg_v7_0_12 | verilog | v_tpg_v7_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_tpg_v8_0_0 | verilog | v_tpg_v8_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_uhdsdi_audio_v1_0_0 | verilog | v_uhdsdi_audio_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_uhdsdi_audio_v1_1_0 | verilog | v_uhdsdi_audio_v1_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_uhdsdi_audio_v2_0_0 | verilog | v_uhdsdi_audio_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_uhdsdi_vidgen_v1_0_1 | verilog | v_uhdsdi_vidgen_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_vcresampler_v1_0_12 | verilog | v_vcresampler_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_vid_in_axi4s_v4_0_9 | verilog | v_vid_in_axi4s_v4_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_vscaler_v1_0_12 | verilog | v_vscaler_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xaui_v12_3_5 | vhdl | xaui_v12_3_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_wrapper_v3_0_4 | vhdl | xbip_dsp48_wrapper_v3_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_utils_v3_0_9 | vhdl | xbip_utils_v3_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xdma_v4_1_2 | verilog | xdma_v4_1_2 | 0 | 697 *
*---------------------------------------------------------------------------------------------------------------------*
* xhmc_v1_0_8 | verilog | xhmc_v1_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xlconcat_v2_1_1 | verilog | xlconcat_v2_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xlconstant_v1_1_5 | verilog | xlconstant_v1_1_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xlslice_v1_0_1 | verilog | xlslice_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xsdbm_v2_0_0 | verilog | xsdbm_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xsdbm_v3_0_0 | verilog | xsdbm_v3_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xxv_ethernet_v2_4_2 | verilog | xxv_ethernet_v2_4_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xxv_ethernet_v2_5_0 | verilog | xxv_ethernet_v2_5_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lib_srl_fifo_v1_0_2 | vhdl | lib_srl_fifo_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lib_fifo_v1_0_12 | vhdl | lib_fifo_v1_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_datamover_v5_1_20 | vhdl | axi_datamover_v5_1_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* amm_axi_bridge_v1_0_4 | verilog | amm_axi_bridge_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_interconnect_v1_1_16 | verilog | axis_interconnect_v1_1_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ats_switch_v1_0_1 | verilog | ats_switch_v1_0_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* audio_formatter_v1_0_0 | verilog | audio_formatter_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi4stream_vip_v1_1_4 | verilog | axi4stream_vip_v1_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_tc_v6_1_13 | vhdl | v_tc_v6_1_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_axi4s_vid_out_v4_0_10 | verilog | v_axi4s_vid_out_v4_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi4svideo_bridge_v1_0_10 | verilog | axi4svideo_bridge_v1_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_accelerator_adapter_v2_1_14 | vhdl | axis_accelerator_adapter_v2_1_14 | 0 | 216 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_broadcaster_v1_1_17 | verilog | axis_broadcaster_v1_1_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_clock_converter_v1_1_19 | verilog | axis_clock_converter_v1_1_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_combiner_v1_1_16 | verilog | axis_combiner_v1_1_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_data_fifo_v1_1_19 | verilog | axis_data_fifo_v1_1_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_data_fifo_v2_0_0 | verilog | axis_data_fifo_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_register_slice_v1_1_18 | verilog | axis_register_slice_v1_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_dwidth_converter_v1_1_17 | verilog | axis_dwidth_converter_v1_1_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_subset_converter_v1_1_18 | verilog | axis_subset_converter_v1_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axis_switch_v1_1_18 | verilog | axis_switch_v1_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_apb_bridge_v3_0_14 | vhdl | axi_apb_bridge_v3_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_bram_ctrl_v4_0_14 | vhdl | axi_bram_ctrl_v4_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_bram_ctrl_v4_1_0 | vhdl | axi_bram_ctrl_v4_1_0 | 0 | 10 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_sg_v4_1_11 | vhdl | axi_sg_v4_1_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_cdma_v4_1_18 | vhdl | axi_cdma_v4_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_clock_converter_v2_1_17 | verilog | axi_clock_converter_v2_1_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_data_fifo_v2_1_17 | verilog | axi_data_fifo_v2_1_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_register_slice_v2_1_18 | verilog | axi_register_slice_v2_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_crossbar_v2_1_19 | verilog | axi_crossbar_v2_1_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_dma_v7_1_19 | vhdl | axi_dma_v7_1_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_protocol_converter_v2_1_18 | verilog | axi_protocol_converter_v2_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_dwidth_converter_v2_1_18 | verilog | axi_dwidth_converter_v2_1_18 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_emc_v3_0_18 | vhdl | axi_emc_v3_0_18 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_epc_v2_0_21 | vhdl | axi_epc_v2_0_21 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lib_bmg_v1_0_11 | vhdl | lib_bmg_v1_0_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_ethernetlite_v3_0_16 | vhdl | axi_ethernetlite_v3_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_ethernet_buffer_v2_0_19 | vhdl | axi_ethernet_buffer_v2_0_19 | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_fifo_mm_s_v4_1_15 | vhdl | axi_fifo_mm_s_v4_1_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_fifo_mm_s_v4_2_0 | vhdl | axi_fifo_mm_s_v4_2_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_firewall_v1_0_6 | verilog | axi_firewall_v1_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* interrupt_control_v3_1_4 | vhdl | interrupt_control_v3_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_gpio_v2_0_20 | vhdl | axi_gpio_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_hwicap_v3_0_22 | vhdl | axi_hwicap_v3_0_22 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_iic_v2_0_21 | vhdl | axi_iic_v2_0_21 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_intc_v4_1_12 | vhdl | axi_intc_v4_1_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_interconnect_v1_7_15 | verilog | axi_interconnect_v1_7_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_master_burst_v2_0_7 | vhdl | axi_master_burst_v2_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_msg_v1_0_4 | vhdl | axi_msg_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_mcdma_v1_0_4 | vhdl | axi_mcdma_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_mm2s_mapper_v1_1_17 | verilog | axi_mm2s_mapper_v1_1_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_mmu_v2_1_16 | verilog | axi_mmu_v2_1_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_pcie_v2_9_0 | vhdl | axi_pcie_v2_9_0 | 0 | 7 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_pcie_v2_9_0 | verilog | axi_pcie_v2_9_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_protocol_checker_v2_0_4 | verilog | axi_protocol_checker_v2_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_quad_spi_v3_2_17 | vhdl | axi_quad_spi_v3_2_17 | 0 | 12 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_sideband_util_v1_0_2 | verilog | axi_sideband_util_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_tft_v2_0_21 | vhdl | axi_tft_v2_0_21 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_tft_v2_0_21 | verilog | axi_tft_v2_0_21 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_timebase_wdt_v3_0_10 | vhdl | axi_timebase_wdt_v3_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_timer_v2_0_20 | vhdl | axi_timer_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_traffic_gen_v2_0_19 | vhdl | axi_traffic_gen_v2_0_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_traffic_gen_v2_0_19 | verilog | axi_traffic_gen_v2_0_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_traffic_gen_v3_0_4 | vhdl | axi_traffic_gen_v3_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_traffic_gen_v3_0_4 | verilog | axi_traffic_gen_v3_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_uart16550_v2_0_20 | vhdl | axi_uart16550_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_uartlite_v2_0_22 | vhdl | axi_uartlite_v2_0_22 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_usb2_device_v5_0_19 | vhdl | axi_usb2_device_v5_0_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_usb2_device_v5_0_19 | verilog | axi_usb2_device_v5_0_19 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_utils_v2_0_5 | vhdl | axi_utils_v2_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_vdma_v6_3_6 | vhdl | axi_vdma_v6_3_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_vdma_v6_3_6 | verilog | axi_vdma_v6_3_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_pipe_v3_0_5 | vhdl | xbip_pipe_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_addsub_v3_0_5 | vhdl | xbip_dsp48_addsub_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_addsub_v3_0_5 | vhdl | xbip_addsub_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_reg_fd_v12_0_5 | vhdl | c_reg_fd_v12_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_addsub_v12_0_12 | vhdl | c_addsub_v12_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_vfifo_ctrl_v2_0_20 | vhdl | axi_vfifo_ctrl_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_vip_v1_1_4 | verilog | axi_vip_v1_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* bs_switch_v1_0_0 | verilog | bs_switch_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* canfd_v2_0_0 | verilog | canfd_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* can_v5_0_21 | vhdl | can_v5_0_21 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cic_compiler_v4_0_13 | vhdl | cic_compiler_v4_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_bram18k_v3_0_5 | vhdl | xbip_bram18k_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mult_gen_v12_0_14 | vhdl | mult_gen_v12_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cmpy_v6_0_16 | vhdl | cmpy_v6_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_mux_bit_v12_0_5 | vhdl | c_mux_bit_v12_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_shift_ram_v12_0_12 | vhdl | c_shift_ram_v12_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_mux_bus_v12_0_5 | vhdl | c_mux_bus_v12_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_gate_bit_v12_0_5 | vhdl | c_gate_bit_v12_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_counter_v3_0_5 | vhdl | xbip_counter_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_counter_binary_v12_0_12 | vhdl | c_counter_binary_v12_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_compare_v12_0_5 | vhdl | c_compare_v12_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* convolution_v9_0_13 | vhdl | convolution_v9_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cordic_v6_0_14 | vhdl | cordic_v6_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cpri_v8_9_2 | vhdl | cpri_v8_9_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* cpri_v8_9_2 | verilog | cpri_v8_9_2 | 0 | 7 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_acc_v3_0_5 | vhdl | xbip_dsp48_acc_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_accum_v3_0_5 | vhdl | xbip_accum_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* c_accum_v12_0_12 | vhdl | c_accum_v12_0_12 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_multadd_v3_0_5 | vhdl | xbip_dsp48_multadd_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* dds_compiler_v6_0_17 | vhdl | dds_compiler_v6_0_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* dft_v4_0_15 | vhdl | dft_v4_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* dft_v4_1_0 | vhdl | dft_v4_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v7_0_10 | vhdl | displayport_v7_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v7_0_10 | verilog | displayport_v7_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v8_0_2 | vhdl | displayport_v8_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v8_0_2 | verilog | displayport_v8_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v8_1_0 | vhdl | displayport_v8_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v8_1_0 | verilog | displayport_v8_1_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v9_0_0 | vhdl | displayport_v9_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* displayport_v9_0_0 | verilog | displayport_v9_0_0 | 0 | 3 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_mult_v3_0_5 | vhdl | xbip_dsp48_mult_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* floating_point_v7_0_15 | vhdl | floating_point_v7_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* div_gen_v5_1_14 | vhdl | div_gen_v5_1_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fir_compiler_v5_2_5 | vhdl | fir_compiler_v5_2_5 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* duc_ddc_compiler_v3_0_14 | vhdl | duc_ddc_compiler_v3_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ernic_v1_0_0 | verilog | ernic_v1_0_0 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* etrnic_v1_0_2 | verilog | etrnic_v1_0_2 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* etrnic_v1_1_1 | verilog | etrnic_v1_1_1 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* fc32_rs_fec_v1_0_8 | verilog | fc32_rs_fec_v1_0_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* fec_5g_common_v1_0_0 | verilog | fec_5g_common_v1_0_0 | 0 | 9 *
*---------------------------------------------------------------------------------------------------------------------*
* fec_5g_common_v1_1_0 | verilog | fec_5g_common_v1_1_0 | 0 | 9 *
*---------------------------------------------------------------------------------------------------------------------*
* fir_compiler_v7_2_11 | vhdl | fir_compiler_v7_2_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* flexo_100g_rs_fec_v1_0_8 | verilog | flexo_100g_rs_fec_v1_0_8 | 0 | 2 *
*---------------------------------------------------------------------------------------------------------------------*
* floating_point_v7_1_7 | vhdl | floating_point_v7_1_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g709_rs_encoder_v2_2_5 | vhdl | g709_rs_encoder_v2_2_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* rs_toolbox_v9_0_6 | vhdl | rs_toolbox_v9_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g709_rs_decoder_v2_2_7 | vhdl | g709_rs_decoder_v2_2_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g709_fec_v2_3_4 | vhdl | g709_fec_v2_3_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g709_fec_v2_4_0 | vhdl | g709_fec_v2_4_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g975_efec_i4_v1_0_16 | vhdl | g975_efec_i4_v1_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* g975_efec_i7_v2_0_17 | vhdl | g975_efec_i7_v2_0_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_200g_rs_fec_v1_0_4 | verilog | ieee802d3_200g_rs_fec_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_25g_rs_fec_v1_0_10 | verilog | ieee802d3_25g_rs_fec_v1_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_400g_rs_fec_v1_0_4 | verilog | ieee802d3_400g_rs_fec_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_50g_rs_fec_v1_0_10 | verilog | ieee802d3_50g_rs_fec_v1_0_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_rs_fec_v1_0_14 | verilog | ieee802d3_rs_fec_v1_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ieee802d3_rs_fec_v2_0_2 | verilog | ieee802d3_rs_fec_v2_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* ldpc_v2_0_2 | verilog | ldpc_v2_0_2 | 0 | 344 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_3gpp_channel_estimator_v2_0_15 | vhdl | lte_3gpp_channel_estimator_v2_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_3gpp_mimo_decoder_v3_0_14 | vhdl | lte_3gpp_mimo_decoder_v3_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_3gpp_mimo_encoder_v4_0_13 | vhdl | lte_3gpp_mimo_encoder_v4_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tcc_encoder_3gpplte_v4_0_14 | vhdl | tcc_encoder_3gpplte_v4_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_dl_channel_encoder_v3_0_14 | vhdl | lte_dl_channel_encoder_v3_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xfft_v7_2_8 | vhdl | xfft_v7_2_8 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_fft_v2_0_17 | vhdl | lte_fft_v2_0_17 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_multacc_v3_0_5 | vhdl | xbip_dsp48_multacc_v3_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_pucch_receiver_v2_0_15 | vhdl | lte_pucch_receiver_v2_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_multadd_v3_0_13 | vhdl | xbip_multadd_v3_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_rach_detector_v3_1_4 | vhdl | lte_rach_detector_v3_1_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lte_ul_channel_decoder_v4_0_15 | vhdl | lte_ul_channel_decoder_v4_0_15 | 0 | 33 *
*---------------------------------------------------------------------------------------------------------------------*
* mailbox_v2_1_11 | vhdl | mailbox_v2_1_11 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mdm_v3_2_15 | vhdl | mdm_v3_2_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* iomodule_v3_0 | vhdl | iomodule_v3_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lmb_bram_if_cntlr_v4_0 | vhdl | lmb_bram_if_cntlr_v4_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* lmb_v10_v3_0 | vhdl | lmb_v10_v3_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* axi_lite_ipif_v3_0 | vhdl | axi_lite_ipif_v3_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* mdm_v3_2 | vhdl | mdm_v3_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* microblaze_mcs_v2_3_6 | vhdl | microblaze_mcs_v2_3_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* multi_channel_25g_rs_fec_v1_0_0 | verilog | multi_channel_25g_rs_fec_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* polar_v1_0_2 | verilog | polar_v1_0_2 | 0 | 187 *
*---------------------------------------------------------------------------------------------------------------------*
* prc_v1_3_1 | vhdl | prc_v1_3_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* processing_system7_vip_v1_0_6 | verilog | processing_system7_vip_v1_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* proc_sys_reset_v5_0_13 | vhdl | proc_sys_reset_v5_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pr_axi_shutdown_manager_v1_0_0 | vhdl | pr_axi_shutdown_manager_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pr_bitstream_monitor_v1_0_0 | vhdl | pr_bitstream_monitor_v1_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* pr_decoupler_v1_0_7 | vhdl | pr_decoupler_v1_0_7 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* quadsgmii_v3_4_5 | vhdl | quadsgmii_v3_4_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* rs_decoder_v9_0_15 | vhdl | rs_decoder_v9_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* rs_encoder_v9_0_14 | vhdl | rs_encoder_v9_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* rxaui_v4_4_5 | vhdl | rxaui_v4_4_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* rxaui_v4_4_5 | verilog | rxaui_v4_4_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* sd_fec_v1_1_2 | verilog | sd_fec_v1_1_2 | 0 | 304 *
*---------------------------------------------------------------------------------------------------------------------*
* sid_v8_0_13 | vhdl | sid_v8_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* spdif_v2_0_20 | vhdl | spdif_v2_0_20 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* srio_gen2_v4_1_5 | vhdl | srio_gen2_v4_1_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* srio_gen2_v4_1_5 | verilog | srio_gen2_v4_1_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* switch_core_top_v1_0_6 | vhdl | switch_core_top_v1_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* switch_core_top_v1_0_6 | verilog | switch_core_top_v1_0_6 | 0 | 40 *
*---------------------------------------------------------------------------------------------------------------------*
* tcc_decoder_3gppmm_v2_0_17 | vhdl | tcc_decoder_3gppmm_v2_0_17 | 0 | 5 *
*---------------------------------------------------------------------------------------------------------------------*
* tcc_encoder_3gpp_v5_0_14 | vhdl | tcc_encoder_3gpp_v5_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tmr_comparator_v1_0_2 | vhdl | tmr_comparator_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tmr_sem_v1_0_6 | vhdl | tmr_sem_v1_0_6 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tri_mode_ethernet_mac_v9_0_13 | vhdl | tri_mode_ethernet_mac_v9_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tri_mode_ethernet_mac_v9_0_13 | verilog | tri_mode_ethernet_mac_v9_0_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tsn_temac_v1_0_3 | vhdl | tsn_temac_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* tsn_temac_v1_0_3 | verilog | tsn_temac_v1_0_3 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* videoaxi4s_bridge_v1_0_5 | verilog | videoaxi4s_bridge_v1_0_5 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* viterbi_v9_1_10 | vhdl | viterbi_v9_1_10 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_ccm_v6_0_15 | vhdl | v_ccm_v6_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_cfa_v7_0_14 | vhdl | v_cfa_v7_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_cresample_v4_0_14 | vhdl | v_cresample_v4_0_14 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_dual_splitter_v1_0_9 | vhdl | v_dual_splitter_v1_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_dual_splitter_v1_0_9 | verilog | v_dual_splitter_v1_0_9 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_enhance_v8_0_15 | vhdl | v_enhance_v8_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_gamma_v7_0_15 | vhdl | v_gamma_v7_0_15 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_osd_v6_0_16 | vhdl | v_osd_v6_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_rgb2ycrcb_v7_1_13 | vhdl | v_rgb2ycrcb_v7_1_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_vid_sdi_tx_bridge_v2_0_0 | verilog | v_vid_sdi_tx_bridge_v2_0_0 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* v_ycrcb2rgb_v7_1_13 | vhdl | v_ycrcb2rgb_v7_1_13 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xbip_dsp48_macro_v3_0_16 | vhdl | xbip_dsp48_macro_v3_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xfft_v9_0_16 | vhdl | xfft_v9_0_16 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xfft_v9_1_1 | vhdl | xfft_v9_1_1 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* xsdbs_v1_0_2 | verilog | xsdbs_v1_0_2 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*
* zynq_ultra_ps_e_vip_v1_0_4 | verilog | zynq_ultra_ps_e_vip_v1_0_4 | 0 | 1 *
*---------------------------------------------------------------------------------------------------------------------*将vivado_lib中的modelsim.ini的库，复制到modelsim根目录下modelsim.ini，注意只读属性。
