Initial lane alignment sequence（ILAS）是包含链路配置信息的序列。对于AD，ILAS要求是4个LMFC长度，对于逻辑设备（FPGA）要求是4~256个LMFC长度，序列要求：
• 每个LMFC的第1个字符为0x1C（K28.0）。
• 每个LMFC的最后1个字符为0x7C（K28.3）。
• 第2个LMFC的第2个字符为0x9C（K28.4）。
• 链路配置从第2个LMFC的第3个字符开始。
链路配置信息说明表如下，包括传输层配置、协议版本、协议子类、是否支持Scrambling和ID等信息。ADJ相关配置定义可以参见上一小节。
| Parameter | Description | Parameter Range | Field | Encoding |
|---|---|---|---|---|
| ADJCNT | Number of adjustment resolution steps to adjust DAC LMFC. Applies to Subclass 2 operation only. | 0 ... 15 | ADJCNT<3:0> | Binary value |
| ADJDIR | Direction to adjust DAC LMFC 0 -- Advance 1 -- Delay Applies to Subclass 2 operation only | 0 ... 1 | ADJDIR<0> | Binary value |
| BID | Bank ID -- Extension to DID | 0 ... 15 | BID<3:0> | Binary value |
| CF | No. of control words per frame clock period per link | 0 ... 32 | CF<4:0> | Binary value* |
| CS | No. of control bits per sample | 0 ... 3 | CS<1:0> | Binary value |
| DID | Device (= link) identification no. | 0 ... 255 | DID<7:0> | Binary value |
| F | No. of octets per frame | 1 ... 256 | F<7:0> | Binary value minus 1 |
| HD | High Density format | 0 ... 1 | HD<0> | Binary value |
| JESDV | JESD204 version 000 -- JESD204A 001 -- JESD204B | 0 ... 7 | JESDV<2:0> | Binary Value |
| K | No. of frames per multiframe | 1 ... 32 | K<4:0> | Binary value minus 1 |
| L | No. of lanes per converter device (link) | 1 ... 32 | L<4:0> | Binary value minus 1 |
| LID | Lane identification no. (within link) | 0 ... 31 | LID<4:0> | Binary value |
| M | No. of converters per device | 1 ... 256 | M<7:0> | Binary value minus 1 |
| N | Converter resolution | 1 ... 32 | N<4:0> | Binary value minus 1 |
| N' | Total no. of bits per sample | 1 ... 32 | N'<4:0> | Binary value minus 1 |
| PHADJ | Phase adjustment request to DAC Subclass 2 only. | 0 ... 1 | PHADJ<0> | Binary value |
| S | No. of samples per converter per frame cycle | 1 ... 32 | S<4:0> | Binary value minus 1 |
| SCR | Scrambling enabled | 0 ... 1 | SCR<0> | Binary value |
| SUBCLASSV | Device Subclass Version 000 -- Subclass 0 001 -- Subclass 1 010 -- Subclass 2 | 0 ... 7 | SUBCLASSV <2:0> | Binary Value |
| RES1 | Reserved field 1 | 0 ... 255 | RES1<7:0> | Binary value |
| RES2 | Reserved field 2 | 0 ... 255 | RES2<7:0> | Binary value |
| CHKSUM | Checksum Σ(all above fields)mod 256 | 0 ... 255 | FCHK<7:0> | Binary value |
传输中上述配置的位域如下：
| Cfg octet no. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| 0 | DID<7:0> | |||||||
| 1 | ADJCNT<3:0> | BID<3:0> | ||||||
| 2 | X | ADJDIR <0> | PHADJ< 0> | LID<4:0> | ||||
| 3 | SCR<0> | X | X | L<4:0> | ||||
| 4 | F<7:0> | |||||||
| 5 | X | X | X | K<4:0> | ||||
| 6 | M<7:0> | |||||||
| 7 | CS<1:0> | X | N<4:0> | |||||
| 8 | SUBCLASSV<2:0> | N'<4:0> | ||||||
| 9 | JESDV<2:0> | S<4:0> | ||||||
| 10 | HD<0> | X | X | CF<4:0> | ||||
| 11 | RES1<7:0> - Set to all X | |||||||
| 12 | RES2<7:0> - Set to all X | |||||||
| 13 | FCHK<7:0> |